mb/google/rauru: Add MIPI panel support with BOE NS130069-M00

Add support for MIPI panel on Sapphire and enable NS130069-M00 as
the default panel. The panel uses TPS65132S as the bias IC, with supply
set to ±5.9V. Add TPS65132S initialization and power-on sequence are
configured according to the specification.

BUG=b:456907241, b:448281461
TEST=Check display initialization log and display are normal
BRANCH=none

Change-Id: I755b63725fe6243a45deff04e8b2fb10162d5f44
Signed-off-by: Xiaokun Qiao <qiaoxiaokun@huaqin.corp-partner.google.com>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/mainboard/google/rauru/Kconfig

@@ -38,6 +38,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
 	select RTC
+	select MIPI_PANEL_BOE_NS130069_M00 if BOARD_GOOGLE_SAPPHIRE
 
 config MAINBOARD_DIR
 	string

src/mainboard/google/rauru/Makefile.mk

@@ -11,8 +11,11 @@ romstage-y += romstage.c
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
 ramstage-y += panel.c
+ramstage-y += panel_tps65132s.c
 ramstage-y += regulator.c
 
+ramstage-$(CONFIG_BOARD_GOOGLE_SAPPHIRE) += panel_sapphire.c
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 subdirs-y += variants/$(VARIANT_DIR)

src/mainboard/google/rauru/gpio.h

@@ -47,6 +47,8 @@
 #define GPIO_AP_EDP_BKLTEN	GPIO(PERIPHERAL_EN4)
 #define GPIO_EN_PP3300_EDP_X	GPIO(PERIPHERAL_EN2)
 #define GPIO_EDP_HPD_1V8	GPIO(EINT13)
+#define GPIO_LCM_RST_1V8_L	GPIO(LCM_RST)
+#define GPIO_EN_PPVAR_MIPI_DISP	GPIO(EINT25)
 
 #define GPIO_I2SI4_BCK		GPIO(I2SIN1_BCK)
 #define GPIO_I2SI4_LRCK		GPIO(I2SIN1_LRCK)

src/mainboard/google/rauru/panel.c

@@ -9,7 +9,7 @@
 #include "gpio.h"
 #include "panel.h"
 
-static void configure_backlight(bool enable)
+void configure_backlight(bool enable)
 {
 	gpio_output(GPIO_AP_EDP_BKLTEN, enable);
 	gpio_output(GPIO_BL_PWM_1V8, enable);
@@ -47,6 +47,9 @@ __weak void fw_config_panel_override(struct panel_description *panel)
 
 struct panel_description *get_active_panel(void)
 {
+	if (CONFIG(BOARD_GOOGLE_SAPPHIRE))
+		return get_panel_description();
+
 	if (CONFIG(BOARD_GOOGLE_RAURU))
 		return &rauru_panel;
 

src/mainboard/google/rauru/panel.h

@@ -3,8 +3,24 @@
 #ifndef __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 #define __MAINBOARD_GOOGLE_RAURU_PANEL_H__
 
+#include <gpio.h>
 #include <soc/display.h>
+#include <soc/i2c.h>
+#include <soc/tps65132s.h>
+
+#define PMIC_TRS65132S_SLAVE	0x3e
+#define PMIC_I2C_BUS		I2C7
+
+struct tps65132s_config {
+	uint32_t i2c_bus;
+	gpio_t en;
+};
 
 uint32_t panel_id(void);
+void configure_backlight(bool enable);
+void tps65132s_power_on(struct tps65132s_cfg *config);
+
+/* Return the MIPI panel description */
+struct panel_description *get_panel_description(void);
 
 #endif /* __MAINBOARD_GOOGLE_RAURU_PANEL_H__ */

src/mainboard/google/rauru/panel_sapphire.c

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/tps65132s.h>
+
+#include "gpio.h"
+#include "panel.h"
+
+static void mipi_panel_power_on(void)
+{
+	struct tps65132s_cfg config = {
+		.i2c_bus = PMIC_I2C_BUS,
+		.en = GPIO_EN_PP3300_EDP_X,
+		.sync = GPIO_EN_PPVAR_MIPI_DISP,
+	};
+	tps65132s_power_on(&config);
+}
+
+static struct panel_description sapphire_panels[] = {
+	[0x09] = {
+		.configure_backlight = configure_backlight,
+		.power_on = mipi_panel_power_on,
+		.name = "BOE_NS130069_M00",
+		.disp_path = DISP_PATH_DUAL_MIPI,
+		.orientation = LB_FB_ORIENTATION_NORMAL,
+	},
+};
+
+struct panel_description *get_panel_description(void)
+{
+	uint32_t id = panel_id();
+	if (id >= ARRAY_SIZE(sapphire_panels))
+		return NULL;
+
+	return &sapphire_panels[id];
+}

src/mainboard/google/rauru/panel_tps65132s.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+#include <soc/regulator.h>
+#include <soc/tps65132s.h>
+#include <soc/mt6363.h>
+
+#include "gpio.h"
+#include "panel.h"
+
+void tps65132s_power_on(struct tps65132s_cfg *config)
+{
+	const struct tps65132s_reg_setting reg_settings[] = {
+		{ PMIC_TPS65132_VPOS, 0x14, 0x1F },
+		{ PMIC_TPS65132_VNEG, 0x14, 0x1F },
+		{ PMIC_TPS65132_DLYX, 0x95, 0xFF },
+		{ PMIC_TPS65132_ASSDD, 0x5B, 0xFF },
+	};
+
+	mt6363_enable_vrf18(true);
+	config->settings = reg_settings;
+	config->setting_counts = ARRAY_SIZE(reg_settings);
+
+	mtk_i2c_bus_init(config->i2c_bus, I2C_SPEED_FAST);
+
+	if (tps65132s_setup(config) != CB_SUCCESS)
+		printk(BIOS_ERR, "Failed to set up tps65132s\n");
+
+	/* DISP_RST_1V8_L */
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 1);
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 0);
+	mdelay(10);
+	gpio_output(GPIO_LCM_RST_1V8_L, 1);
+}

src/soc/mediatek/mt8196/Makefile.mk

@@ -87,6 +87,7 @@ ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
 ramstage-y += ../common/pmif_spmi_v2.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c
+ramstage-y += ../common/tps65132s.c
 ramstage-y += ../common/usb.c usb.c
 
 BL31_MAKEARGS += PLAT=mt8196