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soc/mediatek/mt8196: Align the struct for storing DRAM calibration data

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The current read calibration data flow may cause memory overwrite due to
struct size mismatch, resulting in fast calibration flow failure. Need
to align the struct for storing DRAM calibration data between coreboot
and mtk-dramk repo to prevent memory overwrite.

BUG=b:450724525
TEST=Bootup ok.

Change-Id: Ic59bc9c7f12c454702ba894dea5dce94984e2121
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90354
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Crystal Guo 2025-11-28 10:40:44 +08:00 • committed by Yu-Ping Wu
commit 3bd554feb2
1 changed files with 3 additions and 3 deletions
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6
src/soc/mediatek/mt8196/include/soc/dramc_param.h
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@ -13,7 +13,7 @@
#include <stdint.h>
#include <sys/types.h>
#define DRAMC_PARAM_HEADER_VERSION 4
#define DRAMC_PARAM_HEADER_VERSION 5
struct sdram_params {
/* rank, cbt */
@ -21,7 +21,7 @@ struct sdram_params {
u32 dram_cbt_mode;
u16 delay_cell_timex100;
u8 u18ph_dly;
u8 u18ph_dly[CHANNEL_MAX];
/* duty */
s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
@ -91,7 +91,7 @@ struct sdram_params {
/* tx oe */
u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
u16 tx_oe_offset[DQS_NUMBER_LP5];
};
struct dramc_data {