cpu/x86/Kconfig: Remove SOC_SETS_MSRS option

The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.

Therefore remove it.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune 2025-08-27 14:26:22 +02:00 committed by Felix Held
commit 29bec62a22
2 changed files with 0 additions and 24 deletions

View file

@ -235,13 +235,6 @@ config X86_INIT_NEED_1_SIPI
These newer AMD and Intel platforms don't need the 10ms wait between
INIT and SIPI, so skip that too to save some time.
config SOC_SETS_MSRS
bool
default n
help
The SoC requires different access methods for reading and writing
the MSRs. Use SoC specific routines to handle the MSR access.
config RESERVE_MTRRS_FOR_OS
bool
default n

View file

@ -15,22 +15,6 @@ typedef union msr_union {
} msr_t;
_Static_assert(sizeof(msr_t) == sizeof(uint64_t), "Incorrect size for msr_t");
#if CONFIG(SOC_SETS_MSRS)
msr_t soc_msr_read(unsigned int index);
void soc_msr_write(unsigned int index, msr_t msr);
/* Handle MSR references in the other source code */
static __always_inline msr_t rdmsr(unsigned int index)
{
return soc_msr_read(index);
}
static __always_inline void wrmsr(unsigned int index, msr_t msr)
{
soc_msr_write(index, msr);
}
#else /* CONFIG_SOC_SETS_MSRS */
/* The following functions require the __always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called
@ -61,6 +45,5 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr)
);
}
#endif /* CONFIG_SOC_SETS_MSRS */
#endif /* __ASSEMBLER__ */
#endif /* CPU_X86_MSR_ACCESS_H */