Otherwise flags field is pre-filled with random garbage.
Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This prevents Windows from displaying the IOM device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify IOM device
not shown as unknown device in Device Manager.
Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86257
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This prevents Windows from displaying the PMC device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify PMC device
not shown as unknown device in Device Manager.
Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This is not connected, so update the configuration to
reflect that.
Change-Id: I2922988758e0fa73b4d29ac13380f20f4606cd8e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This causes FSP-M to fail memory training, so disable it.
Change-Id: I4a3544a153d6d4da95c4d679665d9c92bd04ed87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86268
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not use CNVi, so disconnect the unused GPIOs.
Change-Id: I93457ed65e11c9f6f3bff052bb0d82a0389b67c9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The upstream arm-trusted-firmware has removed the DISABLE_PEDANTIC
option in Commit 79eb1aff7850 ("Remove DISABLE_PEDANTIC build option").
Therefore, drop the option for BL31.
Change-Id: Iaca07ce190c566fe79814fd8bbd8821d3ea76955
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rectify board configuration flags based on the schematics Doc.
105-D99700-00C and User Guide #58168 (NDA).
Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85493
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are gobbling up the `$(CC_$(arch))` stderr when testing the
toolchain. This change makes it so we print the command we tried to
invoke and the output from the command.
```
toolchain.mk:183: The coreboot toolchain for 'x86_32' architecture was not found.
toolchain.mk:183: /build/guybrush/tmp/portage/sys-boot/coreboot-9999/files/reclient/ccache /build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-gcc -v
I AM STDERR
toolchain.mk:183: I AM STDOUT
toolchain.mk:219:
toolchain.mk:220: Path to your toolchain is currently set to '/build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin'
toolchain.mk:222:
toolchain.mk:223: To build the entire coreboot toolchain: run 'make crossgcc'
```
BUG=b:392874252, b:389737339
TEST=USE_REMOTEEXEC=true BOARD=brya bazel run @portage//internal/packages/stage2/target/board/chromiumos/sys-boot/coreboot:9999_debug
Change-Id: I7c7352c7254c21deb3e4a03106b841ec9f111ba4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
All 16 IVB PCIe lanes go to one x16 slot without bifurcation.
There is no use for peg11.
Hide it to squelch the leftover devices warning.
Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hide peg12, dev4, and peg60 devices to squelch leftover devices
warning seen with p8z77-m, p8z77-v and p8z77-v_le_plus:
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:00:01.1
[WARN ] PCI: 00:00:01.2
[WARN ] PCI: 00:00:04.0
[WARN ] PCI: 00:00:06.0
[WARN ] PCI: Check your devicetree.cb.
No board in this family can do the 8/4/4 PCIe lane split to
require the peg12 bridge, or implemented dev4 at all.
Only p8c_ws wired up the 4 extra Xeon PCIe lanes peg60 is supposed
to cover, and its overridetree already enables it.
Therefore, be proactive and hide these from the rest of the family.
Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
There is no reason to default to a 1MB CBFS when the descriptor gives us
5MB to work with.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86219
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This is useful when booted with the (not yet mainline) libgfxinit for
Bay Trail.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86218
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Previously only the '06-37-03' and '06-37-09' microcode files were provided
but '06-37-08' was missing.
Linux on my '06-37-08' SOC was segfaulting in various unpredictable ways without
this patch.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Update dxio descriptors based on PI source code 1.2.0.0a.
Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit introduces a new macro, cbfs_add_bmp_file, to the ChromeOS
vendor code Makefile. The macro simplifies the process of adding BMP
files to the CBFS (coreboot Filesystem) by encapsulating the
repetitive tasks of specifying file attributes such as file path,
type, and compression flag.
TEST:Both 'cb_logo.bmp' and 'cb_plus_logo.bmp' files are included with
the same properties, within the coreboot firmware image.
Change-Id: I827451da79931c09768965c3ad071ecdd918d367
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow.
Here is an example, if cse_perf_data.timestamp[i] value is
4304903 milliseconds. When multiplied by 1000 to convert to
microseconds, the value becomes 0x979B58 instead of 0x100979B58.
TEST=Boot to OS
Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86215
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add VBT data file for craaskov, and enable its use by selecting
INTEL_GMA_HAVE_VBT.
VBT extracted from stock firmware image Google_Craaskov.15217.616.0;
it has BDB version 2.51, which matches the current FSP binaries.
TEST=build/boot craaskov with edk2 payload
Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meteor Lake uses the same helper functon as Alder Lake, so
it can be configured via the opton API.
Change-Id: I6d1dc802e672431aa643e318a7cb045f7d6eaa06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option to selected a reduced brightness for the power LED. The
EC code will use this option to write to the relavant offset
accordingly.
Change-Id: I4796e0572a48bca5f9c59e96466416e975cfe8ca
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the memcpy_s function as it is not used.
Additionally, the function did not return the expected values:
0: If the memory copy is successful.
EINVAL: If dest or src is a null pointer, or if count is greater
than RSIZE_MAX.
ERANGE: If count is greater than destsz.
Change-Id: I0d32c838e94ae760907efe55ed00bab3faaaa8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86233
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This GPIO is only used for SATA SSDs so set it as not
connected.
Change-Id: I42c0ec36eee81a849f744a2d03862797f2463921
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The schematic shows that this GPIO is not connected, so
set it as not connected.
Change-Id: Ia62b76055f839c48fc112ca46d8654db5b331cd9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86236
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On boards that do not use SATA, this should be connected.
For boards that do use it, it should be NF5.
Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This value used was just wrong; set the correct one that matches
the verb table.
Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Explicitly set ECT in romstage; enable it for boards that use
LPxxx memory and disable it for boards that use SODIMMs.
Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Correct, and unify, the configuration of the GPIOs use in ACPI
for enabling and resetting:
* Make all GPIOs host owned
* Set enable GPIOs to DEEP
* Set reset GPIOs to PLTRST
Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86205
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not have TBT 4, so unselect Kconfig values
for it.
Change-Id: Id13bb7fc1f9a8f00c10effeaf4b8e1970a173e36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: I757b2c2f77edb21d0eb1a59e3e1eb81671b9929f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: I95c3d1607b62c899acdda6b3b3aae97067e6b266
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BT_EN (VGPIO_0) needs to be host-owned, so that the driver
can control it during the reset procedure. Adjust it accordingly.
Change-Id: I9acc7943de423c0ab441226c0fb4f437a10d2749
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.
Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is proven to be more reliable when resuming from S3.
Change-Id: I479493a384ae1ca880a0caf255ea832b4bb9a366
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
