tree: Use true, false for DspEnable

DspEnable is a boolean, so use true false instead of 0 1.

Change-Id: I5bab9db3632848f92732160bb821dda8cdb14281
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86189
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/51nb/x210/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "false"
 
 	# FSP Configuration
-	register "DspEnable" = "0"
+	register "DspEnable" = "false"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/acer/aspire_vn7_572g/devicetree.cb

@@ -315,7 +315,7 @@ chip soc/intel/skylake
 			register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"	# 17:16 in pmbase+0018h
 		end
 		device ref hda		on
-			register "DspEnable" = "1"
+			register "DspEnable" = "true"
 			# PchHdaDspEndpointDmic is only to be returned to reference code
 			# DXE phase as HOB, used to select blob for NHLT
 		end

src/mainboard/google/eve/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -59,7 +59,7 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/google/glados/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "true"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -37,7 +37,7 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -25,7 +25,7 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -34,7 +34,7 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -34,7 +34,7 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -37,7 +37,7 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -34,7 +34,7 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/skylake
 
 	# FSP Configuration
-	register "DspEnable" = "0"
+	register "DspEnable" = "false"
 	register "ScsEmmcHs400Enabled" = "0"
 
 	register "SerialIoDevMode" = "{

src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb

@@ -4,7 +4,7 @@ chip soc/intel/skylake
 	register "gpe0_dw0" = "GPP_C"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "true"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "3"
 	register "SkipExtGfxScan" = "1"
 

src/mainboard/libretrend/lt1000/devicetree.cb

@@ -27,7 +27,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "false"
 
 	# FSP Configuration
-	register "DspEnable" = "1"
+	register "DspEnable" = "true"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/protectli/vault_kbl/devicetree.cb

@@ -20,7 +20,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "5" # TCC of 95C
 
 	# FSP Configuration
-	register "DspEnable" = "0"
+	register "DspEnable" = "false"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/purism/librem_skl/devicetree.cb

@@ -38,7 +38,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "false"
 
 	# FSP Configuration
-	register "DspEnable" = "0"
+	register "DspEnable" = "false"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/skylake
 	register "dptf_enable" = "false"
 
 	# FSP Configuration
-	register "DspEnable" = "0"
+	register "DspEnable" = "false"
 	register "IoBufferOwnership" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"