vc/intel/fsp: Update PTL FSP headers from 2431.00 to 2454.00

Update generated FSP headers for PantherLake  from 2431.00 to 2454.00

Changes include:
- Update in FspmUpd.h : Adjusted offsets and updated comments.
- Update in FspsUpd.h : Removed C1e and updates offset of the fields

BUG=b:381169612
TEST=Able to build google/fatcat

Change-Id: I788a0d2373593bc7bd447dd37150ec4fda6d6bb4
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85750
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>

src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h

@@ -1737,21 +1737,21 @@ typedef struct {
 
 /** Offset 0x05BF - Reserved
 **/
-  UINT8                       Reserved50[6];
+  UINT8                       Reserved50[7];
 
-/** Offset 0x05C5 - Usage type for ClkSrc
+/** Offset 0x05C6 - Usage type for ClkSrc
   0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
 **/
   UINT8                       PcieClkSrcUsage[18];
 
-/** Offset 0x05D7 - ClkReq-to-ClkSrc mapping
+/** Offset 0x05D8 - ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
 **/
   UINT8                       PcieClkSrcClkReq[18];
 
-/** Offset 0x05E9 - Reserved
+/** Offset 0x05EA - Reserved
 **/
-  UINT8                       Reserved51[47];
+  UINT8                       Reserved51[46];
 
 /** Offset 0x0618 - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -2918,7 +2918,7 @@ typedef struct {
 
 /** Offset 0x0B10
 **/
-  UINT8                       UnusedUpdSpace56[6];
+  UINT8                       UnusedUpdSpace55[6];
 
 /** Offset 0x0B16
 **/