This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions
from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake,
Meteor Lake and Tiger Lake. These definitions are no longer needed.
TEST=Able to build and boot google/xol and google/karis.
Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change removes the unused pch_handle_sideband() function from the
Meteor Lake platform code.
TEST=Able to build and boot google/rex.
Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT.
The design change to follow the brox's GPE0 routing, and the
FP wake source can be routed.
BUG=b:363166664
TEST= Build jubilant firmware
Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial support for the LattePanda Mu board, which features:
- Intel Alder Lake-N N100 processor
- Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory
- Samsung KLMCG2UCTA-B041, 64GB eMMC storage
- SO-DIMM 260-pin connector for function expansion
This commit includes:
- Basic board configuration
- Memory initialization
- Essential I/O setup
- Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file
from original BIOS
- BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu
located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip"
Test Environment:
- Carrier Board: Lite
- Payload: mrchromebox/edk2
- EDK2 Version: uefipayload_202309
Test result
Passed:
- Windows 11 boot from eMMC
- Install Ubuntu 24.04 on NVMe SSD
- Ubuntu 24.04 boot from NVMe SSD
- USB 3.0/2.0 functionality
- Realtek RTL8111H-CG-RH Ethernet
- HDMI Display
- Audio over HDMI work in Ubuntu 24.04
Known Issues:
- S3 sleep mode non-functional
- Power-on after shutdown requires power removal
- SuperIO UART not detected in Windows 11
- Audio over HDMI not work in Windows 11
- Windows 11 BSOD occurs with NVMe SSD installed:
- Stop code: Machine Check Exception
- NVMe SSD not working on Windows 11, except when:
- KDNet Debugging enabled on NIC during boot
- SSD becomes functional in this scenario
Change-Id: I79696bdd837a221860b32f54629212c3346dca66
Signed-off-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Even we assert PRSET# early to save the delay between PERST# assertion
and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe
link up. (1ms delay for each try)
```
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe
reset. So we can de-assert PERST# at early stage to improve the boot
time.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Add support for creating a DSM Method for Intel Bluetooth that
is outlined in Intel's connectivity integrated guide (which has
no document number).
It supports two GUIDs:
Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Tile Activation
Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Bluetooth reset timing
Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the non-vboot boot path, eSPI is configured as part of
fch_pre_init(), and we need to ensure that the mainboard sets the
eSPI GPIOs properly before the common SoC code performs eSPI init.
Use the mb_set_up_early_espi() function to set the eSPI GPIOs at
the correct time.
TEST=build/boot google/zork (morphius), verify keyboard functional.
Change-Id: I03efe6def37a018c3de410523be21bf008174e94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that zork can boot without vboot, ensure that the GPIOs set in
verstage are programmed in bootblock on the non-vboot path.
The eSPI GPIOs will be set in a subsequent patch using
mb_set_up_early_espi() since setting them in
bootblock_mainboard_early_init() would be too late given when the
SoC eSPI init takes place.
TEST=build/boot google/zork (morphius) w/o vboot
Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a new fw config field for wifi category as WIFI_6_8852, which is
PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port
as well as bluetooth port.
BUG=b:356434907
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login
screen, it is because it inserts 12 blank frames if it receives the
unmute in VB-ID.
Always override the mute in VB-ID to avoid Tcon EC detected the
audiomute_flag change.
BUG=b:360243615
BRANCH=firmware-nissa-15217.B
TEST:Verfied on Teliks and cannot reproduce the issue
Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
CAPID_A, BDSM and BGSM registers may not exist on specific platform,
this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER`
to select them.
Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an
empty macro, so there's no problem with that. However, if we would like
to include that file in pre-ramstage, then DEVTREE_CONST would be
'const', leading to the following build error:
```
src/soc/mediatek/common/pcie.c:104:26: error: assignment discards
'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
104 | root_dev = pcidev_path_on_root(devfn);
| ^
```
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Bluetooth driver in kernel requires reset-gpio in current resource
settings (_CRS) and device specific data (_DSD) ACPI objects. Hence
remove ACPI Power Resource for Bluetooth device so that the concerned
ACPI objects get populated.
BUG=b:362817900
TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and
_DSP ACPI objects are filled in the SSDT with the required data.
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x004D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"reset-gpio",
Package (0x04)
{
\_SB.PCI0.XHCI.RHUB.HS10,
Zero,
Zero,
One
}
}
}
})
Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on
the mainboard and likely also routes one USB2 port to the m.2 E key slot
which is typically used for Bluetooth support when an E key m.2 WIFI +
Bluetooth card is installed.
This is untested, since I only have the cw-al-4l-v2.0 mainboard, but
from looking at the documentation of the version 1 and looking at how
things are done on the version 2 this should be correct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.
BUG=none
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field. The bit 15:8 of the returned port ID value should be 0xF2
instead of zero.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1) Add all required changes for eSOL support.
2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo.
The CSOT (MNC207QS1-1) panel is used for the devicetree.
BUG=b:362895813
TEST=On-screen text message seen during MRC training on Trulo SKU1.
MRC: no data in 'RW_MRC_CACHE'
bootmode is set to: 0
DP PHY mode status not complete
DP PHY mode status not complete
DP PHY mode status not complete
...
Informing user on-display of memory training
Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Previously, `early_graphics_stop()` was skipped unconditionally if
`CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led
to overlapping screens when CSE sync was not triggered in ramstage,
as both the eSOL message and the firmware splash screen would be
displayed.
This change refactors the condition for calling `early_graphics_stop()`
to ensure it is only skipped if a CSE firmware update is actually
required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set.
This allows eSOL to display its message during CSE sync, but tears
down early graphics programming in other cases to prevent overlapping
screens.
Additionally, this change ensures that `early_graphics_stop()` is the
last function called by the romstage to guarantee proper cleanup.
BUG=b:362895813
TEST=Able to boot google/tivviks_ufs without overlapping screens.
Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
The file is updated significantly because it wasn't regenerated for a
while.
Change-Id: I2b18cb614f5fc38f2a417f7595475fdedfb6d625
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
How it approximately works:
(During a normal system run):
1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI
runtime
2. If applying the update requires a reboot, EFI implementation creates
a new CapsuleUpdateData* EFI variable pointing at the beginning of
capsules description (not data, but description of the data) and does
a warm reboot leaving capsule data and its description in RAM to be
picked by firmware on the next boot process
(After DEV_INIT:)
3. Capsules are discovered by checking for CapsuleUpdateData* variables
4. Capsule description in memory and capsule data is validated for
sanity
5. Capsule data is coalesced into a continuous piece of memory
(On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:)
6. Buffer with coalesced capsules is marked as reserved
(On BS_WRITE_TABLES via lb_uefi_capsules() hook:)
7. coreboot table entry is added for each of the discovered capsules
(In UEFI payload:)
8. CapsuleUpdateData* get removed
9. coreboot table is checked for any update capsules which are then
applied
Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
By default, QEMU bails when trying to use bigger images mounted with
'-drive if=pflash', which is required to make use of writable flash
introduced in CB:82555. This changes both default size in Kconfig as
well as FMAP layouts.
Since QEMU 5.0.0 it is possible to change the limit of firmware size
with `max-fw-size` machine configuration option, up to 16 MiB, as bigger
sizes would overlap with IO APIC memory range. Default is still 8 MiB,
so it makes sense to have identical default in coreboot.
Error thrown by QEMU when trying to use too big ROM:
qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes
Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82639
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating
Intel chipset. In addition, even though it implements SMI_STS register,
QEMU never sets any bits in it. As there is little emulated hardware
that can be generating SMI, assume that all SMIs come from APM. This
source is used e.g. to disable ACPI (which wasn't working until now on
QEMU) and SMMSTORE.
Tested by invoking SMMSTORE commands from the payload with SMM logging.
Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fspm_rc_heap is already accounted for inside .car.data. Some linkers
like LLD do not like overlapping regions so remove this.
Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84048
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
LTO does not like that assert on a constant, so use the more appropriate
static assertion.
Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On xeon-sp this is a zero length array. With GCC LTO this triggers the
stringop-overread warning. To work around this change the signature of
the function from an array to a pointer.
Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"
Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.
Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GCC LTO incorrectly warns about this it seems.
This also exits gracefully from stage-cache code if no smm region is
found.
Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84040
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no struct device *dev equivalent of this function. Clang LTO
warns about mismatching types.
Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The driver sets ACPI names for PCIe root ports and its subordinate
devices, and fill SSDT for them accordingly. SPR PCIe root port
devices are initially supported.
TEST=Build and boot on intel/archercity CRB
Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
