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soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

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A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"

Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.

Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Arthur Heymans 2024-08-25 11:43:34 +02:00
commit b571e54173
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/meteorlake/meminit.c
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@ -8,7 +8,7 @@
#define LPX_PHYSICAL_CH_WIDTH 16
#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH)
#define DDR5_PHYSICAL_CH_WIDTH 32
#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */
#define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)