tree: Use boolean for s0ix_enable

Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/aoostar/wtr_r1/devicetree.cb

@@ -14,7 +14,7 @@ chip soc/intel/alderlake
 
 	register "dptf_enable" = "1"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	register "common_soc_config" = "{
 		.i2c[0] = {

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -1,5 +1,5 @@
 chip soc/intel/cannonlake
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	register "common_soc_config" = "{
 		/* Touchpad */
 		.i2c[0] = {

src/mainboard/cwwk/adl/devicetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
 	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"

src/mainboard/google/auron/devicetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/broadwell
 	chip cpu/intel/haswell
 		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 
-		register "s0ix_enable" = "1"
+		register "s0ix_enable" = "true"
 	end
 
 	device domain 0 on

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -14,7 +14,7 @@ chip soc/intel/broadwell
 	chip cpu/intel/haswell
 		device cpu_cluster 0 on end
 
-		register "s0ix_enable" = "0"
+		register "s0ix_enable" = "false"
 	end
 
 	device domain 0 on

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/broadwell
 		device cpu_cluster 0 on end
 
 		# Disable S0ix for now
-		register "s0ix_enable" = "0"
+		register "s0ix_enable" = "false"
 
 		register "vr_config" = "{
 			.slow_ramp_rate_set    = 3,

src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable package C state demotion on Raptorlake as a W/A for S0ix issues
 	# seen on J0 and Q0 SKUs

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 	register "gen3_dec" = "0x00fc0901"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "1"

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/alderlake
 	register "gen3_dec" = "0x00fc0901"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable package C state demotion on Raptorlake as a W/A for S0ix issues
 	# seen on J0 and Q0 SKUs

src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/alderlake
 	register "gen3_dec" = "0x00fc0901"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "1"

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -29,7 +29,7 @@ chip soc/intel/alderlake
 	register "gen3_dec" = "0x00fc0901"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "1"

src/mainboard/google/brya/variants/orisa/overridetree.cb

@@ -24,7 +24,7 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw2" = "GPP_F"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "1"

src/mainboard/google/brya/variants/trulo/overridetree.cb

@@ -24,7 +24,7 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw2" = "GPP_F"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "1"

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -145,7 +145,7 @@ chip soc/intel/jasperlake
 	register "SdCardPowerEnableActiveHigh" = "1"
 
 	# Enable S0ix support
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Display related UPDs
 	# Select eDP for port A

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -39,7 +39,7 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	register "dptf_enable" = "1"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 25,

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -53,7 +53,7 @@ chip soc/amd/cezanne
 	}"
 
 	# Enable S0i3 support
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Enable STT support
 	register "stt_control" = "1"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
 	# Enable System Agent dynamic frequency
 	register "SaGv" = "SaGv_Enabled"
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	# Enable DPTF
 	register "dptf_enable" = "1"
 	register "power_limits_config" = "{

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
 	# Enable System Agent dynamic frequency
 	register "SaGv" = "SaGv_Enabled"
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	# Enable DPTF
 	register "dptf_enable" = "1"
 	register "power_limits_config" = "{

src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/meteorlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "1"

src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb

@@ -31,7 +31,7 @@ chip soc/intel/meteorlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "1"

src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/meteorlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "1"

src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb

@@ -31,7 +31,7 @@ chip soc/intel/meteorlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"	# Disable USB-C Port 3
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "1"

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -27,7 +27,7 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	register "dptf_enable" = "1"
 	register "satapwroptimize" = "1"
 	register "power_limits_config" = "{

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	register "dptf_enable" = "1"
 	register "satapwroptimize" = "1"
 	register "AcousticNoiseMitigation" = "1"

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -195,7 +195,7 @@ chip soc/intel/tigerlake
 	register "DdiPort4Ddc" = "0"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Enable DPTF
 	register "dptf_enable" = "1"

src/mainboard/intel/adlrvp/devicetree.cb

@@ -132,7 +132,7 @@ chip soc/intel/alderlake
 	# TCSS USB3
 	register "tcss_aux_ori" = "0"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 	register "dptf_enable" = "1"
 
 	register "serial_io_i2c_mode" = "{

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -95,7 +95,7 @@ chip soc/intel/alderlake
 	# TCSS USB3
 	register "tcss_aux_ori" = "0"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,

src/mainboard/intel/adlrvp/devicetree_n.cb

@@ -70,7 +70,7 @@ chip soc/intel/alderlake
 	register "tcss_aux_ori" = "4"
 	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
 
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,

src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb

@@ -40,7 +40,7 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# Disable S0ix
-	register "s0ix_enable" = "0"
+	register "s0ix_enable" = "false"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge

src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb

@@ -38,7 +38,7 @@ chip soc/intel/cannonlake
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb

@@ -150,7 +150,7 @@ chip soc/intel/jasperlake
 	}"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "VGPIO_39"

src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb

@@ -50,7 +50,7 @@ chip soc/intel/meteorlake
 	register "cnvi_bt_core" = "true"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Disable C1 C-state auto-demotion
 	register "disable_c1_state_auto_demotion" = "1"

src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
 	# S0ix enable
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"		# Type-A Port A0
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"		# Type-A Port A1

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -68,7 +68,7 @@ chip soc/intel/tigerlake
 	register "TcssAuxOri" = "0"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Enable DPTF
 	register "dptf_enable" = "1"

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -75,7 +75,7 @@ chip soc/intel/tigerlake
 	register "TcssAuxOri" = "0"
 
 	# Enable S0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# Enable DPTF
 	register "dptf_enable" = "1"

src/mainboard/prodrive/atlas/devicetree.cb

@@ -20,7 +20,7 @@ chip soc/intel/alderlake
 	register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
 
 	# Disable S0ix
-	register "s0ix_enable" = "0"
+	register "s0ix_enable" = "false"
 
 	# Display configuration (4 DPs)
 	register "ddi_ports_config" = "{

src/mainboard/prodrive/hermes/devicetree.cb

@@ -105,7 +105,7 @@ chip soc/intel/cannonlake
 	register "tcc_offset" = "1"     # TCC of 99C
 
 	# Disable S0ix
-	register "s0ix_enable" = "0"
+	register "s0ix_enable" = "false"
 
 	# Enable Turbo
 	register "eist_enable" = "true"

src/mainboard/protectli/vault_ehl/devicetree.cb

@@ -11,7 +11,7 @@ chip soc/intel/elkhartlake
 	register "eist_enable" = "true"
 
 	# Enable lpss s0ix
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/purism/librem_jsl/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/jasperlake
 
 	register "eist_enable" = "true"
-	register "s0ix_enable" = "0"
+	register "s0ix_enable" = "false"
 
 	register "SaGv" = "SaGv_Enabled"
 

src/mainboard/purism/librem_l1um_v2/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[14]" = "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcClkReq[15]" = "PCIE_CLK_NOTUSED"
 
-	register "s0ix_enable" = "0"
+	register "s0ix_enable" = "false"
 
 	register "eist_enable" = "true"
 

src/mainboard/system76/tgl-u/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/tigerlake
 	register "eist_enable" = "true"
 
 	# Enable s0ix, required for TGL-U
-	register "s0ix_enable" = "1"
+	register "s0ix_enable" = "true"
 
 # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
 	# Enable C6 DRAM

src/soc/intel/elkhartlake/chip.h

@@ -128,7 +128,7 @@ struct soc_intel_elkhartlake_config {
 	uint32_t gen4_dec;
 
 	/* Enable S0iX support */
-	int s0ix_enable;
+	bool s0ix_enable;
 	/* Enable DPTF support */
 	int dptf_enable;
 

src/soc/intel/tigerlake/chip.h

@@ -141,7 +141,7 @@ struct soc_intel_tigerlake_config {
 	uint32_t gen4_dec;
 
 	/* Enable S0iX support */
-	int s0ix_enable;
+	bool s0ix_enable;
 	/* S0iX: Selectively disable individual sub-states, by default all are enabled. */
 	enum lpm_state_mask LpmStateDisableMask;