tree: Use eist_enable as bool for newly merged files

Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2024-08-31 10:27:34 +02:00
commit f3d54feef4
3 changed files with 3 additions and 3 deletions

View file

@ -1,7 +1,7 @@
chip soc/intel/alderlake
# FSP configuration
register "eist_enable" = "1"
register "eist_enable" = "true"
# Sagv Configuration
register "sagv" = "SaGv_Enabled"

View file

@ -13,7 +13,7 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# FSP Silicon
register "eist_enable" = "1"
register "eist_enable" = "true"
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "true"

View file

@ -11,7 +11,7 @@ chip soc/intel/meteorlake
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
register "eist_enable" = "true"
# Thermal
register "tcc_offset" = "8"