KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original
SERIRQ function.
Note that this change breaks Rambi 1.5 keyboard functionality.
BUG=chrome-os-partner:24424
TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB
interrupt toggling removed from EC code.
BRANCH=Rambi, Glimmer, Clapper
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b
Reviewed-on: https://chromium-review.googlesource.com/181757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
1. Clean up some debug messages
2. Remove some dead code
3. Correct some delay time.
BUG=none
BRANCH=none
TEST=build and boot up graphic
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I4362cd886cfd625ef55535839e8ad1a7416977d4
Reviewed-on: https://chromium-review.googlesource.com/181003
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is an emulation cpu.
Lots of stuff missing, clearly, but I want to get the basic outline right.
BUG=None
TEST=breaks no builds
BRANCH=None
Change-Id: Ie9431afe1dbc4eb8e4b5b73da006a0603a221f3f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
- Remove some unused functions from CPU participant that were
confusing the userland component since the CPU does not have
an ACPI managed sensor.
- Guard the charger participant with an ifdef so it can be
left out if not supported.
- Use the EC methods for setting auxiliary trip points and for
handling the event when those trip points are crossed.
- Add _NTT _DTI _SCP methods for thermal sensors. I'm not
clear if these are required or not but they seem to be expected
by the other DPTF framework components.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and load ESIF framework
Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC now supports two auxiliary programmable trip points for
thermal monitoring. These are expected to be used by DPTF and
need to be exported.
In order to support these the header was updated from the latest
chrome ec source.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
BUG=chrome-os-partner:24657
BRANCH=beltino
TEST=build and boot on beltino, suspend and wake with etherwake
Change-Id: Ifef013217c68f88d15e83d6f60de7eb80db8cbe5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181519
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
There's no reason to keep maintaining support on this mainboard, since nobody has one.
BUG=None
TEST=no need to test, it was no longer even used
BRANCH=None
Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180503
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The products having shipped, and living in their own branch,
we might as well enable native graphics since:
1. it works
2. it removes a blob and the only good blob is a dead blob
3. it's faster
4. when we have problems, we can diagnose them more easily
5. when we get to newer kernels the boot time will magically get faster
as the driver realizes graphics is running. Where else do you get a 3-4 second
speedup for free?
BUG=None
BRANCH=None
TEST=Built and booted and saw graphics on peppy and falco
Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181225
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Historically we had set panel timing in the mainboard gma code. This goes
back to the replay-attack video startup.
We can let the haswell gma code set these values from the device tree
settings.
BUG=None
TEST=Build and boot with this change.
BRANCH=None
Change-Id: If32150d2857241ca2d2c88880086f49d25815d76
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180521
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This is always built into coreboot, and is enabled by a static variable
in src/lib/hardwaremain.c. Payload choosing can be enabled at build
time, or at runtime via jtag/gdb.
The operation is simple. The chooser, if enabled, lists the payloads and puts
up a prompt.
Payloads:
fallback/payload
Pick one>
The user then types in the name of a payload, e.g.
Pick one>fallback/payload
The line is ended by newline or carriage return.
And the payload is booted.
If you get it wrong, no backspace
or correction. Just hit return and try again.
I started with Bayou but feel the need is low and the complexity
high for that solution; this is just much simpler.
So, let's think about some UI here. Some options:
- default to the first payload if the user hits return
- time out after 5 seconds or so
- Don't make people type the name;
number the payloads as they are printed and let the user
hit, say, 2, to get the second payload
What would you like to see?
BUG=None
TEST=Works on Nyan
BRANCH=None
Change-Id: I4f93633636abf73e65e1b14c1b9e77ac2e25c453
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180343
Reviewed-by: Puneet Kumar <puneetster@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
eMMC CLK was incorrectly configured as PULL_UP, but should have been
PULL_DOWN. 2K pulls somehow masked this problem.
BUG=chrome-os-partner:24353
TEST=Verify eMMC is bootable on Rambi on boards that previously failed
with an all-20K, all-PU eMMC pin configuration.
BRANCH=None
Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel expects CPUs to be in a known good state at boot, which
means the CPUs are not in reset and not gated. Ungate the clock
and clear the resets for the LP cluster (cluster1) as is done for
the G cluster.
BUG=chrome-os-partner:23816,chrome-os-partner:24487
TEST=No more hangs during cluster switching.
BRANCH=None
Change-Id: I88d80f6072281beb98bba6ae38a0ddeb81165038
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180866
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
BUG=chrome-os-partner:24455
BRANCH=none
TEST=Manual. Run heavy workload on device with fan disabled.
Verify throttling starts at 95C and system shuts down at 99C.
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel does not support using pll_c_out0 as the parent of sclk,
nor does it support the use of super dividers. The reason for this
is that DVFS schemes must use the pre-divided rate with using super
dividers when setting voltages, which makes them essentially useless.
Instead, set pll_c_out1 to 300Mhz (pll_c / 2) and use that as the parent
of sclk.
BUG=chrome-os-partner:24487
TEST=Kernel now boots with sclk DVFS enabled
BRANCH=None
Change-Id: Ia106963d290122cddbaf9eaf88047fda2dfe8b8a
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180865
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
The BISOC.EXIT_SELF_REFRESH_LATENCY field should
not be updated from the default.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180730
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
For choosing payloads we need to be able to read out all the payload
headers. cbfs_payload_headers() delivers names and all the info available
about any payloads.
BUG=None
TEST=builds, tested on Nyan, works fine.
BRANCH=None
Change-Id: If98437819d53cc01d175234fc7429d6aa3383c2c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180352
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Puneet Kumar <puneetster@chromium.org>
This is for the aarch64 architecture. A followon patch will be for the
ARM Ltd. v8 cpu implementation, followed by a mainboard.
This builds but will require the two follow on patches and my recently submitted
cbfstool patch if you wish to see what it looks like.
It is missing critical support for functions such as memcpy, etc. but my goal
is to get an early view of where it is going to the community.
The initial test will be getting it to halt correctly.
BUG=None
TEST=it breaks no builds
BRANCH=None
Change-Id: Ic298fa5c86547bbe3ca0545d338877673219cfd4
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180178
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
As a first step towards removing hardcodes from the FUI support,
change the haswell call to i915_lightup to panel_lightup, and pass the
intel_dp * as a parameter. Get rid of the scalar arguments and make
them part of intel_dp. Get rid of file-scope variables and use the
ones in the intel_dp struct. In falco, use functions that peppy
uses. Drop slippy support for FUI, it's a dead board; if this is ok
I'll remove the files next.
And, incidentally, fix the broken RGBX constant and change it to BGRX.
BUG=None
TEST=build and boot on falco and peppy. Verify that the colors are now correct.
BRANCH=None
Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174932
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
We have no good reason to be handling the TCO timeout
as an SMI since we aren't doing anything special with it
and clearing the status in the handler prevents the reboot
from actually happening.
BUG=chromium:321832
BRANCH=falco,peppy,wolf,leon,beltino,panther,monroe,samus
TEST=boot and read PMBASE+30h and check that bit13 is clear
Change-Id: I074ac0cfa7230606690e3f0e4c40ebc2a8713635
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180672
Rambi's reference code will live at slot 3 in the
verified firmware section.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. Verified correct area where
reference code was loaded from.
Change-Id: I8bee46600429ac8f732fe334852f69aff1324150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180027
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
When employing vboot firmware verification the reference
code loading should load from the verified firmware
section. Add this ability.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted rambi. Noted firmware being loaded
from rw verified area. Also noted S3 resume loading
from cached area.
Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180026
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Certain platforms need to have reference code
packaged and verified through vboot. Therefore,
add this option.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built.
Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180025
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Nyan's SPI chip is capable of dual-output reads, so let's use it.
BUG=none
BRANCH=none
TEST=built and booted on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df
Reviewed-on: https://chromium-review.googlesource.com/177836
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This implements x2 mode when reading CBFS media over SPI.
In theory this effectively doubles our throughput, though the initial
results were almost negligibly better. Using a logic analyzer we see
a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we
want to see further gains here then we'll probably need to tune AHB
arbitration and utilization to eliminate bubbles/stalls when copying
from APB DMA.
BUG=none
BRANCH=none
TEST=built and booted on Nyan.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e
Reviewed-on: https://chromium-review.googlesource.com/177835
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Add a Kconfig variable so that driver code knows whether
or not to use dual-output reads.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5
Reviewed-on: https://chromium-review.googlesource.com/177834
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This reverts commit 58ee4a7f63.
The underlying problem has been fixed by:
ARM: Define custom ELF headers for ARM.
$ cbfstool /build/nyan/firmware/coreboot.rom printcoreboot.rom: 1024 kB, bootblocksize 83968, romsize 1048576, offset 0x18080
alignment: 64 bytes, architecture: arm
Name Offset Type Size
fallback/romstage 0x18080 stage 17556
fallback/coreboot_ram 0x1c580 stage 31509
config 0x24100 raw 2920
(empty) 0x24cc0 null 897752
BUG=None
TEST=Built for nyan and verified that the ROM stage was less than 18KB instead
of being 46KB.
BRANCH=None
Change-Id: I4727f1b3d96a27a6382363565ab3153cec559547
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
At least when building with the gnu toolchain, the headers the linker
automatically generate save space for the actual ELF headers in one of the
loadable segments. This creates two problems. First, the data you intended to
be at the start of the image doesn't actually show up there, it's actually the
ELF headers. Second, the ELF headers are essentially useless for firmware
since there's currently nothing to tell you where they are, and even if there
was, there isn't much of a reason to look at them. They're useful in userspace
for, for instance, the dynamic linker, but not really in firmware.
This change adds a PHDRS construct to each of the linker scripts used on ARM
which define a single segment called to_load which does not have the flag set
which would tell the linker to put headers in it. The first section defined in
the script has ": to_load" to tell the linker which segment to put it in, and
from that point on the other sections go in there by default.
BUG=None
TEST=Built and booted on nyan. Verified that the ROM stage was less than 18KB.
Reverted the change which forced ROM stage alignment and saw that the ROM
stage stayed the same size.
BRANCH=None
Change-Id: Ie2670f33f0421b16b2d4663fbfa99358890c77e4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Remove many no longer needed code and files.
More clean up will be followed.
BUG=none
BRANCH=none
TEST=build and boot up graphic
Change-Id: I72471be01e7c9b5244aff12b45f887dd35dfe58e
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/180135
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Make it clear that we are doing little more than toggling some
GPIOs. Also remove any hint that we think romstage is in RW; that's
some ways off.
BUG=chrome-os-partner:24548
TEST=just a comment change, it still builds.
BRANCH=None
Change-Id: Ie2bd051fb99ed86d588f6dfc2e80aea1edc8f07c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180161
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The ROMSTAGE_BASE currently must be aligned to 0x8000 bytes, otherwise linker
will try to do that and pad zeros, creating a large (ex, >40k) romstage blob,
which cannot be loaded properly.
BUG=none
TEST=Boots successfully on Nyan.
Change-Id: I7626542c8344bbf6641a200879e4aa18183dc1bd
Reviewed-on: https://chromium-review.googlesource.com/180150
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
The kernel iosf driver uses HID INT33BD to probe and
be provided the 12 bytes in PCI for access.
BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, load iosf_mbi driver and
verify that it gets address 0xe00000d0
Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180098
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not used currently on rambi board. Disable in case it
saves power.
BUG=chrome-os-partner:23862
BRANCH=none
TEST=build and boot on rambi
Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180084
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SoC needs to provide a 32k clock signal SUSCLK for
some modems to work properly, so this enables the signal.
BUG=chrome-os-partner:24425
TEST=Manual, check SUSCLK pin with a scope.
Change-Id: I81fcc5a1fd27f4e1261fc761ea6eb017649acfa2
Reviewed-on: https://chromium-review.googlesource.com/180101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
With the ACPI GNVS exported and depthcharge changed to
initialize eMMC in ACPI mode we can now put the SCC
devices into ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot on rambi, test eMMC and SD card
Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To allow doing DRAM initialization in ROM stage instead of BootROM, we need to
move bootblock and ROM stage base address into iRAM, also the stack and CBFS
cache area just like TTB.
BUG=none
TEST=Boots on Nyan without problem.
Change-Id: I459faef5eb0f75561089dafbb111ae83729c3a29
Reviewed-on: https://chromium-review.googlesource.com/179822
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Add iRAM layout in Kconfig comments so we can know how and where to utilize iRAM
in future.
BUG=none
TEST=none # simply adding comments.
Change-Id: I77ec661e6980ad7d77a9c26840bd911a555cc37c
Reviewed-on: https://chromium-review.googlesource.com/179814
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Make sure reg_script is executed before the device is put into
ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi from eMMC in ACPI mode
Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will make it possible for payloads to find the ACPI
NVS region which is needed to get base addresses for devices
that are in ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Correct norrin display specific settings. Drop venice2 supporting
functions.
norrin display code needs to be clean up.
BUG=None
TEST=built, flash and boot, graphic shown up
BRANCH=None
Change-Id: If62028b6f5cb101c4898f7198c3e057f2bac61f3
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/179745
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
In order to use the same reference code on S3 resume
that was booted the program needs to be cached. Piggy
back on the ramstage cache to save the loaded reference
code program.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed. Noted locations of reference
code caching and load addresses in console.
Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179777
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Allow ramstage cache to be used from ramstage proper. Also
add a helper function for checking validity of ramstage
cache structure.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179775
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Certain code paths want to know if S3 resume is
happening. However, the current baytrail code doesn't
note S3 resume early enough. Therefore, mark S3
resume just after pattr setup.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179774
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
