samus: Enable XHCI mode by default

- Enable xhci_default setting in devicetree
- Enable usb_xhci_on_resume setting for PEI
- Enable XHCI driver in libpayload

BUG=chrome-os-partner:23752
BRANCH=none
TEST=emerge-samus chromeos-coreboot-samus

Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180673
This commit is contained in:
Duncan Laurie 2013-12-18 10:55:48 -08:00 committed by chrome-internal-fetch
commit c5ef875f6d
3 changed files with 9 additions and 5 deletions

View file

@ -56,15 +56,15 @@ CONFIG_LP_NVRAM=y
# CONFIG_LP_SPEAKER is not set
# CONFIG_LP_STORAGE is not set
CONFIG_LP_USB=y
CONFIG_LP_USB_UHCI=y
CONFIG_LP_USB_OHCI=y
CONFIG_LP_USB_EHCI=y
# CONFIG_LP_USB_XHCI is not set
# CONFIG_LP_USB_UHCI is not set
# CONFIG_LP_USB_OHCI is not set
# CONFIG_LP_USB_EHCI is not set
CONFIG_LP_USB_XHCI=y
CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_PCI=y
CONFIG_LP_USB_GEN_HUB=y
# CONFIG_LP_USB_MEMORY is not set
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
CONFIG_LP_IO_ADDRESS_SPACE=y

View file

@ -80,6 +80,9 @@ chip northbridge/intel/haswell
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013e0000"
# Route all USB ports to XHCI per default
register "xhci_default" = "1"
device pci 13.0 on end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA

View file

@ -124,6 +124,7 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_xhci_on_resume: 1,
usb2_ports: {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, 0, /* P0: HOST PORT */