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Aaron Durbin 53c42fb1c8 baytrail: cache reference code for S3 resume 
In order to use the same reference code on S3 resume
that was booted the program needs to be cached. Piggy
back on the ramstage cache to save the loaded reference
code program.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed. Noted locations of reference
     code caching and load addresses in console.

Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179777
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2013-12-13 02:44:17 +00:00
..
arch exynos: Install the BL1 and set the checksum in the Makefile. 2013-12-10 03:26:39 +00:00
console ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
cpu x86: Add SMM helper functions to MP infrastructure 2013-10-23 04:08:19 +00:00
device pnp: Allow setting of misc register 0xfa in device tree 2013-11-08 00:52:45 +00:00
drivers tpm: Clean up I2C TPM driver 2013-11-11 23:47:09 +00:00
ec baytrail: Basic DPTF framework 2013-12-11 19:50:19 +00:00
include ramstage_cache: allow ramstage usage add valid helper 2013-12-13 00:07:08 +00:00
lib ramstage_cache: allow ramstage usage add valid helper 2013-12-13 00:07:08 +00:00
mainboard rambi: Enable DPTF 2013-12-11 19:50:23 +00:00
northbridge haswell: Report x32 memory as "x8 or x32" 2013-10-23 21:27:19 +00:00
soc baytrail: cache reference code for S3 resume 2013-12-13 02:44:17 +00:00
southbridge lynxpoint: Add SATA DEVSLP disable option 2013-11-15 04:58:50 +00:00
superio pnp: Allow setting of misc register 0xfa in device tree 2013-11-08 00:52:45 +00:00
vendorcode baytrail: Add support for LPSS and SCC devices in ACPI mode 2013-12-11 19:50:27 +00:00
Kconfig Fix the reg_script stuff to not be used in ARM builds and not break them. 2013-11-02 01:07:13 +00:00