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Revert "tegra124: Fix bloated ROM stage."

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This reverts commit 58ee4a7f63.

The underlying problem has been fixed by:
ARM: Define custom ELF headers for ARM.

$ cbfstool /build/nyan/firmware/coreboot.rom printcoreboot.rom: 1024 kB, bootblocksize 83968, romsize 1048576, offset 0x18080
alignment: 64 bytes, architecture: arm

Name                           Offset     Type         Size
fallback/romstage              0x18080    stage        17556
fallback/coreboot_ram          0x1c580    stage        31509
config                         0x24100    raw          2920
(empty)                        0x24cc0    null         897752

BUG=None
TEST=Built for nyan and verified that the ROM stage was less than 18KB instead
of being 46KB.
BRANCH=None

Change-Id: I4727f1b3d96a27a6382363565ab3153cec559547
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-12-14 05:17:41 -08:00 • committed by chrome-internal-fetch
commit a1761f24e9
1 changed files with 3 additions and 4 deletions
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7
src/soc/nvidia/tegra124/Kconfig
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@ -37,8 +37,8 @@ config BOOTBLOCK_CPU_INIT
# +4000 (Coreboot) Stack.
# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
# point address specified in BCT).
# +0000 (Coreboot) Bootblock (max 40k).
# +A000 (Coreboot) ROM stage (max 32k).
# +0000 (Coreboot) Bootblock (max 36k).
# +9000 (Coreboot) ROM stage (max 36k).
# 0x4002_0000 (Coreboot) Cache of CBFS.
# 0x4003_FFFF End of iRAM.
@ -62,10 +62,9 @@ config BOOTBLOCK_BASE
hex
default 0x4000e000
# Note ROMSTAGE_BASE must be aligned to 0x8000.
config ROMSTAGE_BASE
hex
default 0x40018000
default 0x40017000
config RAMSTAGE_BASE
hex