Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF| AM:0000000081C60000--0000000081C7FFFF| s | | 00001000| read/write access exec | yes| inn| non-cacheable | 1| no | \\ramstage\Global\_dram_aop_cmd_db'
Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ramdump is a debug image loaded during a crash to capture memory
contents for post-crash analysis. This patch adds support for
loading this image during the qclib_rerun() sequence.
Key changes:
1) Introduce QC_RAMDUMP_ENABLE Kconfig option to control ramdump image
loading.
2) Add qclib_check_dload_mode() as a weak function that works in
conjunction with the Kconfig check to decide whether the ramdump
image should be loaded.
3) Add new CBFS file entry and table entry definition for ramdump_meta.
4) Re-use "apdp_ramdump_meta" region for ramdump metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I42bcd74c3d236a6af49ec4b548bc9cda33bd0825
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90306
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces a new Kconfig option, QC_APDP_ENABLE, to control
Application Processor Debug Policy (APDP) image loading. When this
option is enabled, the APDP image is loaded during the
qclib_load_and_run() sequence. It also adds a new CBFS file entry and
table entry definition for apdp_meta, along with a memory region symbol
apdp_ramdump_meta for metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I8d0847c99a1129359f2c758b7a07b9c022f1c8c8
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90303
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to reserve 33 MB DRAM memory for display in memlayout.ld
file.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Basic device boot functionality with the specified memory reservation
has been validated. Display functionality has not yet been tested, as
the display driver porting is yet to be done.
Change-Id: I49a4a20b9869bc5cf0b11f4eb6cff7865bb2e761
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API, spmi_read_bytes(), to allow reading a
sequence of registers from a Qualcomm PMIC using the SPMI bus.
While the existing spmi_read8() is suitable for single-byte
access, reading large log areas (like the PON history log)
requires iterating over a contiguous block of addresses. This
new function encapsulates the required loop, calling spmi_read8()
sequentially for each address in the range.
This abstraction improves code cleanliness and makes high-level PMIC
log parsing much simpler.
Key changes:
- Define spmi_read_bytes() prototype in qcom_spmi.h.
- Implement spmi_read_bytes() in spmi.c to perform sequential
reads using spmi_read8().
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I6017336a882a8fa8d771b0127e78dd4f0fdbdd0e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the SPMI_ADDR macro to wrap both the slave and reg
arguments in parentheses.
The previous definition, ((slave << 16) | reg), led to incorrect
address calculation when the slave argument was an arithmetic or
logical expression (e.g., (a | b)), as the bit-shift operator (<<)
has higher precedence than the logical OR (|).
The revised macro guarantees that the full slave expression is
evaluated before the bit shift, ensuring correct SPMI register
address construction.
Key changes:
- Wrap slave and reg arguments in parentheses within
SPMI_ADDR definition.
BUG=b:439819922
TEST=Verify that the SPMI_ADDR output is correct.
e.g. SPMI_ADDR(0x02 | 0x01, 0x200)
Output before this change:
```
((0x02 | 0x01 << 16) | 0x200)
(0x02 | 0x010000 | 0x200)
(0x010202)
```
Output after this change:
```
(((0x02 | 0x01) << 16) | 0x200)
(((0x03) << 16) | 0x200)
((0x030000) | 0x200)
(0x030200)
```
Change-Id: I58b36b62f0b5a59c03a1c1d08640fe9086d81d7a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to configure DFSR table, introduce qupv3_clock_v2
structure to calculate register addresses for serial engines 2
and 3. Update CBCR registers to use the new structure for QUPv3
clock enablement.
BUG=b:444617760
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Dump DFSR registers for corresponding QUP and check if values are
updated properly into correct register address.
Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.
Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.
The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.
This is necessary for DMA operations that occur after DRAM is
initialized.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Instrument the Qualcomm QCLib flow with timestamps to measure
execution time for both the initial loading/running phase and the
subsequent re-entry phase.
The timestamps are placed as follows:
- TS_QUALCOMM_QCLIB_INIT_START/END: Tracks the execution of
`qclib_load_and_run()`.
- TS_QUALCOMM_QCLIB_REINIT_START/END: Tracks the execution of
`qclib_rerun()`, which typically handles the AOP bring-up.
This instrumentation helps in profiling and optimizing the boot
performance on Qualcomm platforms.
Change-Id: I200ea5a78f4630000e80aed6dc38581af4d2e8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90112
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.
Changes include:
- Declaring new memory regions in symbols_common.h.
- Defining base addresses and sizes for these regions in memlayout.ld.
- Marking these regions as reserved in soc_read_resources() to
prevent overwrites by coreboot.
- Modifying CBMEM top address.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).
The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.
The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.
w/o this patch
```
[ERROR] Unable to load previous training data.
```
w/ this patch
```
[WARN ] qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```
Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce a new static function, `qclib_debug_log_level`, that
checks a runtime-configurable option, "qclib_debug_level", to
control whether QCLib enables serial logging.
This allows for dynamic control of QCLib's verbose output via a
coreboot option instead of relying solely on the static
`CONFIG(CONSOLE_SERIAL)` Kconfig option. This is necessary because
while the serial console might be enabled for general coreboot
logging, the user may want to suppress the often extensive and
low-level output from QCLib to keep the console clean during normal
operations.
The check for enabling QCLib's serial output is updated from
`if (CONFIG(CONSOLE_SERIAL))` to
`if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())`
The option value is read using
`get_uint_option("qclib_debug_level", 1)`, meaning the default
behavior is to enable QCLib logging if `CONSOLE_SERIAL` is set,
maintaining backward compatibility unless the option is explicitly
set to 0 at runtime.
BUG=b:445211186
TEST=Build and boot a Qualcomm platform with CONFIG_CONSOLE_SERIAL
enabled. Confirmed QCLib logs are present by default.
Set option "qclib_debug_level" to 0 via CBFS option and confirmed
QCLib logs are suppressed while coreboot serial output remains
active.
Change-Id: I2c7326fae889508f09e1eb5e3863456cf54f5c29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.
TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.
Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.
Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `SSRAM_START/END`, `BSRAM_START/END`, and `AOPSRAM_START/END`
macros were redefined across multiple Qualcomm SoC `memlayout.ld` files.
To reduce code duplication and improve maintainability, this commit
moves these common macros into the shared `<soc/memlayout.h>` header
part of the Qualcomm common code.
The SoC-specific linker scripts are updated to remove the local
definitions.
TEST=Built for all affected SoCs (qcs405, sc7180, sc7280, x1p42100)
Change-Id: I8638b8e03e1e51f57b7e91a072f3d9cdb4ec6200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88782
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the DRAM memory layout to reserve additional
regions critical for platform functionality and debugging. It
consolidates several CPUCP-related memory areas and adds new
reservations for Ramdump and Shared Memory.
- Ramdump and Shared Memory: New reserved regions, dram_ramdump and
dram_smem, are added to protect memory used for crash dumps and
inter-processor communication.
- CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions
are consolidated into a single, contiguous dram_cpucp region from
0x80A00000 to 0x815A0000. This simplifies the memory map and
optimizes resource allocation.
Reserving these regions is crucial to prevent other bootloader stages
or the kernel from overwriting critical firmware data, which could lead
to unexpected behavior or system instability.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel.
Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stating with Qualcomm X1P42100 SoC generation, the DRAM memory map is
not expected to be contiguous (unlike previous generations) therefore,
the memory map could be something like this.
1. Assume hardware design has 4GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (2 GB) : 0x880000000 - 0x900000000
2. Assume hardware design has 16GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (14 GB) : 0x880000000 - 0x400000000
3. Assume hardware design has 64GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (30 GB) : 0x880000000 - 0x1000000000
- DDR_SPACE_2 (32 GB) : 0x8800000000 - 0x9000000000
This commit introduces logic to handle systems with fragmented DRAM
configurations. Previously, the Memory Management Unit (MMU) was
configured assuming a single, contiguous block of DRAM.
This change extends the MMU setup to properly configure multiple,
non-contiguous DRAM regions.
The changes include:
- Declaring dram_space_1 and dram_space_2 as optional regions, allowing
the dynamic allocation for these DRAM ranges based on DRAM capacity of
the platform.
- Introduce `qc_get_soc_dram_space_config` function that takes care of
DRAM based resource splitting as per `_dram`, `_dram_space_1` and
`_dram_space_2` region limit.
- Modifying qc_mmu_dram_config_post_dram_init() to check for these
optional regions and configure them individually. This ensures all
available DRAM is correctly mapped and accessible to the system.
This approach improves flexibility and allows coreboot to support a
wider range of Qualcomm platforms with different memory layouts.
TEST=Able to boot google/quenbi to OS.
Change-Id: If3788f4c77535f9a5e47ad2034ab9a8e0fe85b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88752
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the qc_mmu_dram_config_post_dram_init function
to remove the ddr_base parameter. The function can now retrieve the
base address of the DRAM from the ddr_region global variable, which
is already available.
TEST=Able to build and boot google/quenbi.
Change-Id: I97159dee6a035ed3e38cbfca1e44b8e671d15fc1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.
The changes involve:
- Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
and dram_tz_rem in the symbols_common.h header.
- Defining the base addresses and sizes for these new regions in
memlayout.ld.
Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.
TEST=Able to load aop firmware while booting google/quenbi without
boot hang.
Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds support to skip DDR training when valid training data
is available in flash.
The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.
TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.
w/o this patch: doing RW_MRC_CACHE update in every boot.
```
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
```
w/ this patch: no need to perform RW_MRC_CACHE update.
```
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG] read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```
Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.
A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.
This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.
TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.
w/o this patch:
```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm UuI5�ፕ�ѥ���������ͥ��х�����jm UuI5���ѥ���ፕ�ѥ��m��jm UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG] NCC Frequency bumped to 1.363(GHz)
```
w/ this patch:
```
[NOTE ] coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] Silver Frequency bumped to 1.5168(GHz)
[DEBUG] L3 Frequency bumped to 1.1904(GHz)
```
Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to pack aop_meta into CBFS and load QcLib DTB,
SHRM metadata, and AOP metadata. It also populates the QcLib interface
table with these information for firmware authentication and execution.
TEST=Verify presence of AOP metadata file in the CBFS and QcLib
interface table content.
Change-Id: I1a74d9ffbfc10023b0e5610d54218909b18efa01
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I8a3cb1b21e712e588f641f70c040a2334faf0031
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.
Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.
Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed
by different controllers. Previously, the generic `spi_qup_ctrlr`
was hardcoded to manage buses 0 through 15.
Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be
`QUPV3_SE_MAX - 1`.
TEST=Able to build google/herobrine.
Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Refactor the initialization logic for the optional QUPv3 wrapper 2.
Add a runtime check of the `QUP_WRAP2_BASE` macro's value within
`qupv3_fw_init`.
This approach simplifies the QUP wrapper 2 initialization, making the
code flow depend directly on whether a valid base address is defined
for the target SoC.
To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as
a dummy entry) for SoCs like sc7180 and sc7280 which do not include
this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly
evaluate to false for these platforms, skipping the initialization.
Platforms that do have QUP wrapper 2 should define its non-zero base
address.
TEST=Able to build google/herobine.
Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Replace the magic number 0x00000001 with the BIT(0) macro for
QCLIB_GA_ENABLE_UART_LOGGING. This improves readability and
maintainability by clearly indicating that a specific bit is being set.
TEST=Able to build google/herobrine.
Change-Id: Ie425a68c6721343ca53eb883d6278decca92bcad
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The memory log we get returned by QcLib contains Windows line endings
("\r\n"), while we prefer to have POSIX line endings in the CBMEM
console (just "\n"). Filter the '\r' character out when copying that log
into the CBMEM console to convert.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0652300c2393fbc0b3c9875bb0ca1aa921e59098
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77722
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
