Put the GPIOs into groups with clear comments.
Change-Id: I7246fee8bdf111bc08c1335a90609e94356fc611
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
GPIOs, like the USB overcurrent ones, are not used so configure them accordingly.
Change-Id: If5138ccd6048f006408d5335439e7a0143c9cc28
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I693cfecdb73a20b76fa040500eed5d904b857710
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the configuration for the vGPIOs, as it is not needed because
FSP handles it.
Change-Id: I8831379ffd8c9df00736cb62512e023592d0d301
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Byte Mk III is the same, apart from using the Twin Lane N355 instead
of the N200, which means 99.99% of the code is the same.
Change-Id: Ia31f905bea7a6efdad1ed4e36361059ceea2a1ed
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This version of the VBT works for Alder Lake N and Twin Lake.
Change-Id: Ia2161a04018ec3e222a2751b42fe63637b05e6dd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87895
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds
to TCSS port0. In order for the DP functions of the two Type-C ports
to operate normally, the corresponding relationship needs to be
configured correctly.
BUG=b:418106736
TEST=DP function of Type-C0/C1 workable
Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87899
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch removes the power limit override code from google/ocelot until the power limits for WCL are known. It is left as a TODO till then.
Change-Id: I15bd1a1c8397957df96a97b4f9f3de0fd5f5c7f6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Use the storage type from fw_config to determine which types of storage
need to be set up in the payload.
BUG=b:379008996
BRANCH=none
TEST=input "cbi set 6 0x40000000 4" in ec console, and see the
following log:
fw_config match found: STORAGE=STORAGE_UFS2X
storage_setup: eMMC: no, UFS: yes
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ieada3c56b0f69cc1ea3dab4e64641bfc2ba2a0fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87923
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Skywalker reference design supports multiple storage types, such as UFS
and eMMC. We only need to configure eMMC if the board storage type is
eMMC.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I7c3a2e3f7acf75d57d72cda3c9d2e83b77c72f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87922
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add the initialization in romstage.
BUG=b:410763782
BRANCH=none
TEST=Check the CPU frequencies are changing and not fixed values by
using the following commands in kernel:
1) set policy*/scaling_governor as "ondemand"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy6/scaling_governor"
2) Check the CPU frequencies by repeating the command
"grep . /sys/devices/system/cpu/cpufreq/policy*/scaling_cur_freq"
The result is like
/sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:650000
/sys/devices/system/cpu/cpufreq/policy6/scaling_cur_freq:2350000
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Ie64ebd1b78096c38c4398572cbed3e2e9ac6b8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This are a bit illogical, so tidy them up.
Change-Id: Idd4f616181949780c042142344b3bbbccc4f15f6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87894
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add serial_io_i2c_mode to fix can not boot up to OS issue.
2. Change level from low to high to fix parade touchscreen issue.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: Ic0a02daa39f4d1d0287115ecab12f45201704227
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87909
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bootblock size for the Google Bluey mainboard has been increased
from 96KB to 120KB.
This change is necessary to accommodate the growing size of the
bootblock image, which now exceeds the previous 96KB limit. This
expansion ensures that the complete bootblock code, including critical
initialization routines and potentially new features, fits within its
allocated flash region.
TEST=Able to build google/quenbi.
Change-Id: I7bf2c8c6c540327f1b4233ee5ba4e0703d1200f9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for
RT1019.RT1019 and RT9123 use the same GPIOs on the Skywalker reference
design, so the same function is used to improve code reusability. Also
pass the corresponding GPIO to the payload.
BUG=b:417083722
BRANCH=none
TEST=Build pass and test with Depthcharge change:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/6437675
Check audio cmd in depthcharge with:
firmware-shell: AUDIO CMD=audio 500 100 1
Change-Id: I512cd5c8635d08c6b6c54f04d11bf87c64d1b843
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S
for ALC5645. Also pass the corresponding GPIO to the payload.
BUG=b:359705470
BRANCH=none
TEST=build ok and test audio cmd ok
AUDIO CMD=audio 500 100 1
Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>
Change-Id: Ib53175f559eecb3d8b5104b12dabfd4793f65d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Modify USB related settings according to the proto schematic diagram.
BUG=b:409254508
BRANCH=none
TEST=emerge-nissa coreboot chromeos-bootimage,tested USBA and TYPEC function is ok.
Change-Id: I48ec269b612602578b35eeaedffd1a3d311bb97e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87834
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit populates the `board_id()` and `sku_id()` functions
for the Google Bluey mainboard, replacing the previous placeholder
implementations.
- The Board ID (`board_id()`) is now determined by reading a set of
four GPIO pins (GPIO138 as MSB, GPIO137, GPIO136, GPIO135 as LSB)
and interpreting their states as a base-3 encoded value using
the `gpio_base3_value()` helper.
- The SKU ID (`sku_id()`) is retrieved from the Google ChromeEC
by calling `google_chromeec_get_board_sku()` when a ChromeEC
is configured (`CONFIG(EC_GOOGLE_CHROMEEC)`).
Both ID values are cached after their initial determination to
avoid redundant reads.
BUG=b:404985109
TEST=Able to build google/bluey
Change-Id: Ic5a084e35b33a82fef76f33c2663aba7a48c16a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit updates the devicetree for the Google Bluey mainboard
to include entries for the WLAN and SSD PCI devices.
These devices are located on the x1p42100 SoC's PCI domain 0:
- WLAN: device pci 04.0
- SSD: device pci 06.0
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: If0a9491f4178ee9a44c04aea1330b6522dfd9bf0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87859
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit addresses the GPIO configuration for DDR5 on Intel's
PTLRVP mainboard. Specifically, it extends support for the DDR5
configuration by adding a case for PTLP_DDR5_RVP in the GPIO
differential table function. This modification ensures proper handling
of GPIO settings when DDR5 memory is configured, thereby improving
system stability and compatibility.
BUG=none
TEST=Boot with DDR5 configuration.
Change-Id: I3745c0a25e84a0f41dced44613cfd638c12fb1d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87872
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Extracted from coreboot-Google_Craask.15217-841-0.bin
Change-Id: I07d4e7fe63ff6ad43806d73d9e31ffe0aa8807c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87867
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extracted from coreboot-Google_Teliks.15217.734.0.bin
Change-Id: Ib9f077cdd0536e6315b05775337bf30555562cc8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Remove GPP_D16, GPP_D17, and GPP_B25 as they aren't used in ocelot.
Change GPP_A08 polarity in gpio_table and rom_gpio_table.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: Ife444cef816ca2b69db466661c63935f72836554
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:419161631#comment1
BUG=b:419161631
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: If79e58fa52ecb4626fdd6a25e8e3bf6e3c556c6b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87878
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify pujjolo vairant codes for type-c port1 display, parade
touch screen, especially for gpio to fit Trulo. Follow the setting of pujjocento.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I285cd33de6e18a2ffb30eb6401c03f6a4b20dc4a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87843
Reviewed-by: Talal Sadak <tsadak@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
WWAN_FCPO == GPP_D6
WWAN_RST == GPP_E17
spec reuqest: 0 < toff <10ms
LTE is controlled by bits 14 and 15 in fw_config, and P sensor
and LTE modules exist at the same time, so we use the same bit
to control whether to load the driver.
BUG=b:419325064,b:417105553
TEST=Confirm the measured WWAN power sequence
Change-Id: Ia978aef2cc721b65618ac78c13930447d1557797
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87841
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no powering-on control in the fingerprint kernel driver.
Follow Rauru to power-on FP MCU in the FW.
BUG=b:401396071
BRANCH=none
TEST=ectool --name=cros_fp version can get the FP FW version.
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Change-Id: I20ff175ee4874c4188b7d07ee57330a9275dcb3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Moonbuggy.13324.803.0.bin
coreboot-Google_Scout.13324.645.0.bin
Since all variants now have VBTs, move the selection of
INTEL_GMA_HAVE_VBT to the baseboard.
TEST=build/boot various puff variants, including scout.
Change-Id: I2bb06894fc4df358cc38a4627de9f95289c2c5e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Ocelot does not support GEN5 NVME Storage. However since ocelot code
was forked from fatcat, these configs exist in coreboot.
Furthermore, the GEN4 NVME GPIOs have changed for ocelot -
1. GPP_B10 to GPP_H18 - GEN4_SSD_PWREN renamed to EN_PP3300_SSD
2. GPP_B09 to GPP_A08 - M2_GEN4_SSD_RESET_N renamed to SSD_PERST_L
BUG=b:419731962
Change-Id: I005d1188138ac7b4bbffa1437bba9aea39aff117
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update gpio configuration for GPP_A08, GPP_E17, and GPP_F18 to
match ocelot schematic.
Change GPP_H16 (WWAN_PWR_EN) to GPP_E01 (EN_WWAN_PWR) in fw_config.c.
Change GPP_V06 and GPP_V11 to "No Connect" as they are test points.
Change trace names from "SNDW3_" to "SDW3_" to match names on ocelot
schematic.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I8996dc1b2b0f85490d55a86dc2ca6a90c1604638
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87750
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently Francka cannot boot up immediately by pressing power button
when its power state is S5.
This patch fixes the power on process for this scenario.
BUG=b:419406610
BRANCH=none
TEST=Francka boots up immediately by pressing power button in S5.
Change-Id: I52fba7f58faa890955cd07728a6790520df29321
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87807
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This modification sets the HDA GPIO pin to NC by default.
Different audio configurations can be enabled via fw_config.
BUG=b:417133565
TEST=emerge-fatcat coreboot, HDA sound cards can be detected.
Change-Id: I0090a68d86de1067697d7efbb64c4638476c64ca
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87810
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. Also
set AP_HDMI_RST_ODL to low, which is the only open-drain output pin.
BUG=b:397102113
BRANCH=none
TEST=build pass
Change-Id: I4375c25768de8f1462c491b2c84b9cf31f118126
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87796
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the CPU little core frequency from 1.6 GHz to 2.0 GHz to
speed up the boot process.
BUG=b:379008996
BRANCH=none
TEST=check little core cpu frequency is 2GHz in kernel by commands
clkdbg() { echo $@ > /proc/clkdbg ; cat /proc/clkdbg ; }
clkdbg fmeter
See the little core CPU frequency:
fm_armpll_ll_ck : 1999968
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I979f44e9340ea5bd733dc7f0fe47af47a4f403b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87795
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.
BUG=b:396030112
BRANCH=none
TEST=reboot pass. `powerinfo` shows S0 in EC console.
Change-Id: Ib7e9eaa19d232a37b3793bcbe268ba021e456ac7
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
