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mb/google/ocelot/var/ocelot: fix storage configs for ocelot

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Ocelot does not support GEN5 NVME Storage. However since ocelot code
was forked from fatcat, these configs exist in coreboot.

Furthermore, the GEN4 NVME GPIOs have changed for ocelot -
1. GPP_B10 to GPP_H18 - GEN4_SSD_PWREN renamed to EN_PP3300_SSD
2. GPP_B09 to GPP_A08 - M2_GEN4_SSD_RESET_N renamed to SSD_PERST_L

BUG=b:419731962

Change-Id: I005d1188138ac7b4bbffa1437bba9aea39aff117
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Avi Uday 2025-05-23 12:43:55 +05:30 • committed by Matt DeVillier
commit 2117ed850f
2 changed files with 9 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

31
src/mainboard/google/ocelot/variants/ocelot/fw_config.c
View file

@ -179,15 +179,15 @@ static const struct pad_config wwan_disable_pads[] = {
/* Gen4 NVME: at the top M.2 slot */
static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
/* GPP_B10: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_B10, 0, PLTRST),
/* GPP_H18: EN_PP3300_SSD */
PAD_CFG_GPO(GPP_H18, 0, PLTRST),
};
static const struct pad_config gen4_ssd_pads[] = {
/* GPP_B10: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_B10, 1, PLTRST),
/* GPP_B09: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_B09, 1, PLTRST),
/* GPP_B10: EN_PP3300_SSD */
PAD_CFG_GPO(GPP_H18, 1, PLTRST),
/* GPP_B09: SSD_PERST_L */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
};
static const struct pad_config ufs_enable_pads[] = {
@ -195,19 +195,6 @@ static const struct pad_config ufs_enable_pads[] = {
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
};
/* Gen5 NVME: at the bottom M.2 slot */
static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
/* GPP_B16: GEN5_SSD_PWREN */
PAD_CFG_GPO(GPP_B16, 0, PLTRST),
};
static const struct pad_config gen5_ssd_pads[] = {
/* GPP_B16: GEN5_SSD_PWREN */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
/* GPP_E03: M2_GEN5_SSD_RESET_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
};
static const struct pad_config peg_x4slot_wake_disable_pads[] = {
/* GPP_D24: PEG_SLOT_WAKE_N */
PAD_NC(GPP_D24, NONE),
@ -459,11 +446,8 @@ void fw_config_configure_pre_mem_gpio(void)
if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
}
/*
@ -495,13 +479,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
}

7
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
View file

@ -34,8 +34,7 @@ fw_config
field STORAGE 13 14
option STORAGE_UNKNOWN 0
option STORAGE_NVME_GEN4 1
option STORAGE_NVME_GEN5 2
option STORAGE_UFS 3
option STORAGE_UFS 2
end
field FP 15
option FP_ABSENT 0
@ -546,8 +545,8 @@ chip soc/intel/pantherlake
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
register "srcclk_pin" = "6"
device generic 0 on end
end