mb/trulo/var/pujjolo: Modify pujjolo variant
Modify pujjolo vairant codes for type-c port1 display, parade touch screen, especially for gpio to fit Trulo. Follow the setting of pujjocento. BUG=b:395763555 BRANCH=none TEST=Build and boot to pujjolo. Verify functions work. Change-Id: I285cd33de6e18a2ffb30eb6401c03f6a4b20dc4a Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87843 Reviewed-by: Talal Sadak <tsadak@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Luca Lai
Subrata Banik
parent
aea05e51a7
commit
91ebbb8d35
4 changed files with 477 additions and 66 deletions
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@ -2,8 +2,8 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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@ -8,68 +8,138 @@
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/* Pad configuration in ramstage for Pujjolo */
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static const struct pad_config override_gpio_table[] = {
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
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/* A7 : SLP_S0_GATE */
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/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
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/* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */
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/* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */
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/* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */
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/* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */
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/* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
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/* A5 : ESPI_ALERT0# ==> NC */
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PAD_NC(GPP_A5, NONE),
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : NC ==> SLP_S0_GATE_R */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : WWAN_RF_DISABLE_ODL */
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/* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A9 : ESPI_CLK ==> ESPI_SOC_CLK */
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/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
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/* A11 : EN_SPK_PA ==> NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : NC# ==> SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE),
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/* A12 : SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A18 : DDSP_HPDB ==> DDI2_HPD */
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/* A14 : USB_OC1# */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A15 : USB_OC2# */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : USB_OC3# ==> NC */
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PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
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/* A17 : NC */
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PAD_NC(GPP_A17, NONE),
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/* A18 : NC ==> HDMI_HPD_SRC*/
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A20 : HDMI_HPD */
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : USB_C1_AUX_DC_P */
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/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
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/* A22 : USB_C1_AUX_DC_N */
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/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
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/* A23 : NC */
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/* A23 : GPP_A23 ==> NC */
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PAD_NC(GPP_A23, NONE),
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/* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2 : NC */
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PAD_NC(GPP_B2, NONE),
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/* B5 : SOC_I2C_SUB_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* B6 : SOC_I2C_SUB_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* B3 : CPU_GP2 ==> GYRO_SENSOR_INT */
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PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> ACC_SENSOR_INT */
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PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
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/* B5 : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* B6 : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* B7 : GPP_B7 ==> NC */
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PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : WWAN_SAR_DETECT_2_ODL */
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PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
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/* B11 : SOC_PMC_PD0_INT_ODL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* B9 : Not available */
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PAD_NC(GPP_B9, NONE),
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/* B10 : Not available */
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PAD_NC(GPP_B10, NONE),
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/* B11 : SOC_PD0_INT# */
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* B16 : GPP_B16 ==> I2C_5_SDA */
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/* B12 : SLP_S0# ==> PM_SLP_S0# */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
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/* B14 : ACZ_SPKR */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* B15 : NC */
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PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
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/* B16 : GPP_B16 ==> I2C_TOUCHPAD_SDA */
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PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
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/* B17 : GPP_B17 ==> I2C_5_SCL */
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/* B17 : GPP_B17 ==> I2C_TOUCHPAD_SCL */
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PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
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/* C1 : SMBDATA ==> USI_RST_L */
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/* B18 : GPP_B18 ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* B19 : Not available */
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PAD_NC(GPP_B19, NONE),
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/* B20 : Not available */
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PAD_NC(GPP_B20, NONE),
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/* B21 : Not available */
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PAD_NC(GPP_B21, NONE),
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/* B22 : Not available */
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PAD_NC(GPP_B22, NONE),
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/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
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PAD_NC(GPP_B23, NONE),
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, NONE),
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/* C3 : EN_PP3300_UCAM_X */
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PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
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/* C4 : TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* C6 : I2C_SOC_PMC_PD_SCL */
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/* C5 : SML0ALERT# ==> GPP_C5_STRAP */
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PAD_NC(GPP_C5, NONE),
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/* C6 : SML1_SMBCLK */
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/* C7 : I2C_SOC_PMC_PD_SDA */
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/* C7 : SML1_SMBDATA */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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/* D1 : SEN_MODE2_EC_ISH_INT_ODL */
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
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/* E7 : NC ==> FP_RST_ODL */
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PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
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/* D2 : NC ==> EN_FP_PWR */
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PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
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/* D3 : WCAM_RST_L ==> NC */
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/* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* D2 : NC */
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PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> WCAM_RST_L */
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PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
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/* D5 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
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//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : NC */
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PAD_NC(GPP_D5, NONE),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
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/* D9 : NC */
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
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PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
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/* D11 : NC */
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PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
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/* D13 : UART0_ISH_RX_DBG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : UART0_ISH_TX_DBG_RX */
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@ -82,54 +152,152 @@ static const struct pad_config override_gpio_table[] = {
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* D18 : NC ==> UART_AP_TX_FP_RX */
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* D19 : NC */
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/* D19 : WWAN_SAR_DETECT_2_ODL ==> NC */
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PAD_NC(GPP_D19, NONE),
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/* E0 : NC ==> SOC_PEN_DETECT_R_ODL */
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/* E0 : SOC_PEN_DETECT_R_ODL */
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PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
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/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
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PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
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/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
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PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
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/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* E4 : WLAN_WWAN_COEX_1 temp out high*/
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PAD_CFG_GPO(GPP_E4, 0, DEEP),
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/* E5 : WLAN_WWAN_COEX_2 temp out high */
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PAD_CFG_GPO(GPP_E5, 0, DEEP),
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/* E11 : TCHSCR_INT_ODL */
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/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
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PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
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/* E7 : NC ==> FP_RST_ODL */
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PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
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/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
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PAD_CFG_GPO(GPP_E8, 1, DEEP),
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/* E9 : NC */
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PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
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/* E10 : EN_PP3300_WLAN_X */
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PAD_CFG_GPO(GPP_E10, 0, DEEP),
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/* E11 : TCHSCR_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
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/* E13 : SD_WAKE_N */
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
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/* E13 : SD_WAKE_N*/
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PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
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/* E14 : DDSP_HPDA ==> EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : NC */
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PAD_NC(GPP_E15, NONE),
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/* E16 : NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
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/* E18 : NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* E22 : USB_C0_AUX_DC_P */
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/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
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PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
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/* E23 : USB_C0_AUX_DC_N */
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/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
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PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
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/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
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/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
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/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
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/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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/* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
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/* F6 : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* F7 : GPP_F7 ==> GPP_F7_STRAP */
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PAD_NC(GPP_F7, NONE),
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/* F8 : Not available */
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PAD_NC(GPP_F8, NONE),
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/* F9 : Not available */
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PAD_NC(GPP_F9, NONE),
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/* F10 : GPP_F10 ==> GPP_F10_STRAP */
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PAD_NC(GPP_F10, NONE),
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/* F11 : NC ==> GSPI_PCH_CLK_FPMCU */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
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/* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
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/* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
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/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
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/* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
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/* F16 : NC ==> GSPI_PCH_CS_FPMCU_R_L */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
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/* H8 : I2C_1_SDA */
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/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
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PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
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/* F19 : Not available */
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PAD_NC(GPP_F19, NONE),
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/* F20 : Not available */
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PAD_NC(GPP_F20, NONE),
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/* F21 : Not available */
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PAD_NC(GPP_F21, NONE),
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/* F22 : NC */
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PAD_NC(GPP_F22, NONE),
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/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
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PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
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/* H0 : GPP_H0_STRAP */
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PAD_NC(GPP_H0, NONE),
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/* H1 : GPP_H1_STRAP */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* H2 : GPP_H2_STRAP */
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
|
||||
PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
|
||||
/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* H8 : MIPI_WCAM_SDA */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
/* H9 : I2C_1_SCL */
|
||||
/* H9 : MIPI_WCAM_SCL */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
/* H15 : PD0_SOC_DBG_L */
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H12 : GPP_H12 ==> NC */
|
||||
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
|
||||
/* H13 : GPP_H13 ==> NC */
|
||||
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
|
||||
/* H14 : Not available */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
//PAD_CFG_GPI_LOCK(GPP_H15, NONE, LOCK_CONFIG),
|
||||
/* H17 : PD1_SOC_DBG_L*/
|
||||
//PAD_CFG_GPI_LOCK(GPP_H17, NONE, LOCK_CONFIG),
|
||||
/* H16 : Not available */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18 : CPU_C10_GATE_L */
|
||||
/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19 : SOC_I2C_SUB_INT_ODL */
|
||||
/* H19 : SAR_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
|
||||
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H20, 1, DEEP),
|
||||
/* H21 : WWAN_PERST_L */
|
||||
PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
|
||||
/* H23 : WWAN_SAR_DETECT_ODL ==> NC */
|
||||
PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
|
||||
/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
/* R0 : HDA_HP_BCLK_R */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
/* R1 : HDA_HP_SYNC_R */
|
||||
|
|
@ -146,12 +314,107 @@ static const struct pad_config override_gpio_table[] = {
|
|||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
/* S0 : NC */
|
||||
/* S0 : I2S_SPK_BCLK_R ==> NC */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1 : NC */
|
||||
/* S1 : I2S_SPK_LRCK_R ==> NC */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2 : NC */
|
||||
/* S2 : DMIC_CKL_A0 ==> NC */
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
/* S3 : DMIC_DATA0 ==> NC */
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
/* S4 : NC */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5 : NC */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6 : NC */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7 : NC */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
/* I5 : NC */
|
||||
PAD_NC(GPP_I5, NONE),
|
||||
/* I7 : EMMC_CMD ==> NC */
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
/* I8 : EMMC_DATA0 ==> NC */
|
||||
PAD_NC(GPP_I8, NONE),
|
||||
/* I9 : EMMC_DATA1 ==> NC */
|
||||
PAD_NC(GPP_I9, NONE),
|
||||
/* I10 : EMMC_DATA2 ==> NC */
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
/* I11 : EMMC_DATA3 ==> NC */
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
/* I12 : EMMC_DATA4 ==> NC */
|
||||
PAD_NC(GPP_I12, NONE),
|
||||
/* I13 : EMMC_DATA5 ==> NC */
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
/* I14 : EMMC_DATA6 ==> NC */
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
/* I15 : EMMC_DATA7 ==> NC */
|
||||
PAD_NC(GPP_I15, NONE),
|
||||
/* I16 : EMMC_RCLK ==> NC */
|
||||
PAD_NC(GPP_I16, NONE),
|
||||
/* I17 : EMMC_CLK ==> NC */
|
||||
PAD_NC(GPP_I17, NONE),
|
||||
/* I18 : EMMC_RESET# ==> NC */
|
||||
PAD_NC(GPP_I18, NONE),
|
||||
/* GPD0 : BATLOW# ==> SOC_BATLOW_L */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1 : ACPRESENT ==> SOC_ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2 : EC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
|
||||
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* GPD4 : SLP_S3# ==> SLP_S3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5 : SLP_S4# ==> SLP_S4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6 : SLP_A# ==> NC */
|
||||
PAD_NC(GPD6, NONE),
|
||||
/* GPD7 : GPD7_STRAP */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8 : SUSCLK ==> PCH_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9 : NC */
|
||||
PAD_NC(GPD9, NONE),
|
||||
/* GPD10 : SLP_S5# ==> NC */
|
||||
PAD_NC(GPD10, NONE),
|
||||
/* GPD11 : NC */
|
||||
PAD_NC(GPD11, NONE),
|
||||
/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
|
||||
/* vCNV_BT_UART_TXD */
|
||||
PAD_NC(GPP_VGPIO_6, NONE),
|
||||
/* vCNV_BT_UART_RXD */
|
||||
PAD_NC(GPP_VGPIO_7, NONE),
|
||||
/* vCNV_BT_UART_CTS_B */
|
||||
PAD_NC(GPP_VGPIO_8, NONE),
|
||||
/* vCNV_BT_UART_RTS_B */
|
||||
PAD_NC(GPP_VGPIO_9, NONE),
|
||||
/* Configure the unused vUART for Bluetooth pads to NC mode. */
|
||||
/* vUART0_TXD */
|
||||
PAD_NC(GPP_VGPIO_18, NONE),
|
||||
/* vUART0_RXD */
|
||||
PAD_NC(GPP_VGPIO_19, NONE),
|
||||
/* vUART0_CTS_B */
|
||||
PAD_NC(GPP_VGPIO_20, NONE),
|
||||
/* vUART0_RTS_B */
|
||||
PAD_NC(GPP_VGPIO_21, NONE),
|
||||
/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
|
||||
/* BT_I2S_BCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SYNC */
|
||||
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SDO */
|
||||
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SDI */
|
||||
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
|
||||
/* SSP2_SCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
|
||||
/* SSP2_SFRM */
|
||||
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
|
||||
/* SSP_TXD */
|
||||
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
|
||||
/* SSP_RXD */
|
||||
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
|
||||
|
||||
};
|
||||
|
||||
|
|
|
|||
111
src/mainboard/google/brya/variants/pujjolo/memory.c
Normal file
111
src/mainboard/google/brya/variants/pujjolo/memory.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg variant_memcfg = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.rcomp = {
|
||||
/* Baseboard uses only 100ohm Rcomp resistors */
|
||||
.resistor = 100,
|
||||
},
|
||||
|
||||
/* DQ byte map */
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
|
||||
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
|
||||
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
|
||||
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
|
||||
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
|
||||
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
|
||||
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
},
|
||||
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xff,
|
||||
},
|
||||
|
||||
.ect = 1, /* Early Command Training */
|
||||
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &variant_memcfg;
|
||||
}
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
/*
|
||||
* Memory configuration board straps
|
||||
* GPIO_MEM_CONFIG_0 GPP_E1
|
||||
* GPIO_MEM_CONFIG_1 GPP_E2
|
||||
* GPIO_MEM_CONFIG_2 GPP_E3
|
||||
*/
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_E1,
|
||||
GPP_E2,
|
||||
GPP_E3,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
bool variant_is_half_populated(void)
|
||||
{
|
||||
/*
|
||||
* Ideally half_populated is used in platforms with multiple channels to
|
||||
* enable only one half of the channel. Alder Lake N has single channel,
|
||||
* and it would require for new structures to be defined in meminit block
|
||||
* driver for LPx memory configurations. In order to avoid adding new
|
||||
* structures, set half_populated to true. This has the same effect as
|
||||
* having single channel with 64-bit width.
|
||||
*/
|
||||
return true;
|
||||
}
|
||||
|
||||
void variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
|
||||
spd_info->cbfs_index = variant_memory_sku();
|
||||
}
|
||||
|
|
@ -163,6 +163,23 @@ chip soc/intel/alderlake
|
|||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 5d on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PARA3408""
|
||||
register "generic.desc" = ""Parade Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.reset_off_delay_ms" = "2"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||
register "generic.stop_delay_ms" = "280"
|
||||
register "generic.stop_off_delay_ms" = "2"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 24 on end
|
||||
end
|
||||
chip drivers/generic/gpio_keys
|
||||
register "name" = ""PENH""
|
||||
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
|
||||
|
|
@ -287,8 +304,7 @@ chip soc/intel/alderlake
|
|||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 10 on
|
||||
end
|
||||
device i2c 10 on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "3"
|
||||
|
|
@ -314,8 +330,7 @@ chip soc/intel/alderlake
|
|||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 0C on
|
||||
end
|
||||
device i2c 0C on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
|
|
@ -343,8 +358,7 @@ chip soc/intel/alderlake
|
|||
register "nvm_width" = "0x10"
|
||||
register "nvm_compat" = ""atmel,24c08""
|
||||
|
||||
device i2c 50 on
|
||||
end
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
|
|
@ -385,6 +399,25 @@ chip soc/intel/alderlake
|
|||
end
|
||||
device ref ufs on end
|
||||
device ref igpu on
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "4"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) for port C1
|
||||
register "device[3].name" = ""DD03""
|
||||
register "device[3].use_pld" = "true"
|
||||
register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
|
|
@ -416,6 +449,7 @@ chip soc/intel/alderlake
|
|||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
|
|
@ -427,6 +461,11 @@ chip soc/intel/alderlake
|
|||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -475,7 +514,6 @@ chip soc/intel/alderlake
|
|||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
|
|
@ -535,8 +573,7 @@ chip soc/intel/alderlake
|
|||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on
|
||||
end
|
||||
device spi 0 on end
|
||||
end # FPMCU
|
||||
end
|
||||
end
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue