There are 3 banks of GPIOs that need to be described
with specific _UID and memory/interrupt values.
BUG=chrome-os-partner:24314
BRANCH=none
TEST=build and boot on rambi, check for probed driver:
gpiochip_find_base: found new base at 154
gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
gpiochip_find_base: found new base at 126
gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
gpiochip_find_base: found new base at 82
gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02
fed0c000-fed0cfff : INT33FC:00
fed0c000-fed0cfff : INT33FC:00
fed0d000-fed0dfff : INT33FC:01
fed0d000-fed0dfff : INT33FC:01
fed0e000-fed0efff : INT33FC:02
fed0e000-fed0efff : INT33FC:02
Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These panel numbers provided by the OEM.
The old display will stop working.
BUG=None
TEST=builds. I'll test when I get a unit.
BRANCH=None
Change-Id: I6020f0c725d44c4b69d5806e0dfc8da125686baf
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177958
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The xmalloc wrapper checks whether the malloc succeeded, and if not stops
execution and prints a message. xmalloc always returns a valid pointer. The
xzalloc wrapper does the same thing, but also zeroes the memory before
returning it.
BUG=None
TEST=Used this function in nyan, built and booted on it.
BRANCH=None
Change-Id: I00e7de04a5c368ab3603530b98bd3e3596e10632
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178001
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now
Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.
Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
BUG=chrome-os-partner:24258
TEST=built/booted on Norrin/Nyan1 OK, loaded 3.10 kernel, and
did a shutdown -r. Next boot was OK.
Note that if other regs in the PMIC need to be (re)initialized,
it's a simple matter of adding more entries to the init_reg table.
Change-Id: I8cb4721da90673216f0a771d72c6d81590532837
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178226
Reviewed-by: David Hendricks <dhendrix@chromium.org>
If a programming error is detected, die can be used to print a message and
stop execution similar to failing an assert. There's also a "die_if" function
which is conditional.
die functions, like asserts, should be used to trap programming errors and not
when the hardware does something wrong. If all code was written perfectly, no
die function would ever be called. In other words, it would be appropriate to
use die if a function was called with a value that was out of bounds or if
malloc failed. It wouldn't be appropriate if an external device doesn't
respond.
In the future, the die family of functions might print a stack trace or show
other debugging info.
BUG=None
TEST=Used the die_if function in other code and verified that it stops
execution, prints messages like printf, shows file, line, and function
information, and is correctly gated by its condition.
BRANCH=None
Change-Id: I653fc8cb0b4e459522f1b86f7fac280836d57916
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178000
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This adds some delay to allow for the SPI controller to copy data
from the Rx register to the FIFO.
This is intended to complement a similar patch in Depthcharge.
BUG=chrome-os-partner:24215
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idc12f8a835e7e6529724254948684bd05cafdac1
Reviewed-on: https://chromium-review.googlesource.com/177832
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This pin is active low and resets the SOC and TPM. It leaves the memory alone
so that panic info can be discovered by the kernel once the reboot is
complete.
BUG=chrome-os-partner:24098
TEST=With a corresponding change in depthcharge, verified that depthcharge can
reboot the SOC using this GPIO.
BRANCH=None
Change-Id: I101dbb712c458b88213e2254fd1893a1284d1491
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177965
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This print isn't really useful and consumes a lot of time (~13ms)
during copying phases.
BUG=none
BRANCH=none
TEST=Built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I2f32dc097dd3d2b53edd739124f4317f2f91ad71
Reviewed-on: https://chromium-review.googlesource.com/177833
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
The AHB burst length was being set to an invalid value. Apparently
this didn't hurt anything, but we may as well set it correctly.
Also, we don't need to explicitly set AHB_SEQ_WRAP since it defaults
to the value we want.
BUG=none
BRANCH=none
TEST=built and booted on Nyan rev. 0 and 1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Iffb9edeb178ab48876f891d0822a24daae93aa8e
Reviewed-on: https://chromium-review.googlesource.com/177564
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch activates -ffunction-sections and -fdata-sections for the
compiler and --gc-sections for the linker. This will strip out all
unused functions and static/global variables from the final binaries and
reduce the amount of data we need to read over SPI.
A quick test with ToT images shows a 2.5k (13%) / 10k (29%) / 12k (28%)
reduction on Nyan and 3k (38%) / 23k (50%) / 13k (29%) on Pit,
respectively for bootblock / romstage / ramstage.
BUG=None
TEST=Made sure Nyan and Pit still boot to kernel.
Change-Id: I052411d4ad190d0395921ac4d4677341fb91568a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177111
This doesn't seem to be truly necessary, but it matches what other drivers do
and might be a good idea for safety's sake.
BUG=chrome-os-partner:24138
TEST=Built and booted on norrin.
BRANCH=None
Change-Id: Ie7c2717e81b2a5dcb831e608eb56347709dc1483
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177638
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
On nyan boards, the hardware flow control pins for the UART aren't used or
connected to anything, but the reset pinmux settings still have them routed
out some of the SOC pins. That can break input over the serial console if the
pin is pulled in the wrong direction.
Also, if the RX line isn't connected to anything, ie if no servo is connected,
then we don't want it to float around and potentially draw power through the
input pin buffering logic. We add a pull up to it so it will go somewhere in
particular if otherwise unattached.
This is generally not a great place to put pinmux configuration because it's
specific to a particular board but this is shared by everything with a
tegra124 in it. It's a good idea to have serial output as soon as possible,
though, and the other serial related pinmux settings were probably put here
before we really understood the complexities and flexibility of the tegra
pinmux. We might want to factor out this part of the serial console config and
delegate it to a hook in the mainboard specific code, or just wait until we
call bootblock_mainboard_init.
BUG=chrome-os-partner:24138
TEST=Built and booted on a peppy based nyan. Before this change serial input
was ignored. After this change, serial input was accepted by both the firmware
and the kernel.
BRANCH=None
Change-Id: Ie5428500aa525a600eb1ff4a81b5cc2805d5cc92
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177637
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Instead of choosing between SDRAM configurations for rev0 nyans and everything
else (currently only rev1), we should create a kconfig for each possible config
and put them inside a "choice" block. That way we can have an arbitrarily large
number of choices without them getting to be hard to manage or accidentally not
being mutually exclusive. This also makes the choice of SDRAM config more
explicit instead of it being implied by what rev you're compiled for.
One tradeoff of this approach is that you need to know which config goes with
which rev. Unfortunately we can't decide using the board ID like we can for
most other things because the BCT is consumed by code we don't control before
any of our own code runs.
We default to the slower config for safety's sake, because it will work on
both boards, and because it's the right config for the norrin which we were
going to transition to soon anyway.
Also, we can eliminate the NYAN_IN_A_PIXEL kconfig variable. Alas, we hardly
knew ye.
BUG=None
TEST=Built and booted on both types of nyan.
BRANCH=None
Change-Id: I9a630189e001e95c740c6741057511bf5939fdbb
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177580
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Use the board ID to figure out how to initialize the PMIC instead of using a
config option.
BUG=None
TEST=Built and booted on both types of nyan.
BRANCH=None
Change-Id: I26f735f3c7ba910fd237a1d00d616d3d89b9fbd9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177489
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
We can use that to figure out which revision of nyan we're running on and make
some small adjustments for the differences in hardware.
BUG=None
TEST=Built and booted on both versions of nyan.
BRANCH=None
Change-Id: Iaedbc36dcc8e27b95b1e1ec5687bd9592c49d775
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177488
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This sets the sclk:hclk:pclk ratio to 1:2:2 which allows faster
transfers from peripherals to memory.
Performance-wise this currently decreases ramstage loading time
by about 20ms and payload loading time by 35ms.
BUG=chrome-os-partner:24182
BRANCH=none
TEST=Built and booted on Nyan rev 1 and 0. No longer see long
delays in between bytes when transferring >64 bytes via SPI.
CQ-DEPEND=CL:177578
Change-Id: I5812122bf6312a1ab490945c6e52fa3372e86fc9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177563
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
NCORE pad addresses were wildly wrong due to documentation bugs.
BUG=chrome-os-partner:24179
TEST=Manual on Rambi. Verify display isn't always on. Verify brightness
control now works in Chrome OS.
BRANCH=None.
Change-Id: I464436a58baa4957329c11231c5a866dafd97ce8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177597
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The memory clock set up for the pixel based nyan boards is too fast for the
peppy based boards. We want to use the right config for the right board, so
that needs to be configurable based on what board your targeting.
This CL makes the SDRAM BCT config configurable based on whether your nyan is
in a pixel case, and also adds a slower config for us on norrin.
BUG=None
TEST=Built with settings for each board. Used bct_dump to verify that the
settings matched the current config.
BRANCH=None
Change-Id: Ibf1335ac3c9eb488d3753e41c5c9c40c9eda3d56
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177487
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
It turns out that kconfig will silently ignore settings to a variable that
doesn't have a prompt, meaning that this variable was always off no matter
what the config said.
BUG=None
TEST=Before this change, saw that CONFIG_NYAN_IN_A_PIXEL was always off no
matter how it was set in the config. Afterwards, saw that the value followed
the setting in the config.
BRANCH=None
Change-Id: I6f003c4bc2fbaea013a3f1e328280e64fbe7479d
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177486
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The level shifting between 3.3V and 1.8V for the SERIRQ
signal is not working. Instead use the SERIRQ pad as
a gpio which is used as a direct IRQ signal for the
keyboard interupt.
BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi. Keyboard works with associated EC change.
CQ-DEPEND=CL:177189
Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177223
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Some boards need to override which IRQ the i8042 keyboard
controller has its interrupt on instead of the default
IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard
an ability to override the interrupt location.
BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi using this option. New IRQ is correctly
picked up by kernel allowing keyboard support.
Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf
Reviewed-on: https://chromium-review.googlesource.com/177222
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e)
BUG=none
BRANCH=none
TEST=boot tested on Panther
Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452
Reviewed-on: https://chromium-review.googlesource.com/177474
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
The exception_test() mechanism might have been useful when exceptions
were first implemented, but now that they are pretty stable it's really
not necessary anymore (especially not on every single boot in production
Chromebooks). It forces a simple unaligned access, and as we start
having exceptions in stages that might not have paging turned on yet,
it's better to remove that completely.
Also removed the duplicated implementations of SCTLR-stuff and switched
to the existing ones in cache.h.
BUG=None
TEST=Made sure Pit and Nyan still boot and can trigger exceptions in all
stages.
Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177101
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
This patch adds stub implementations of exception_init() to all archs
so that it can be called from src/lib/hardwaremain.c. It also moves/adds
all other invocations of exception_init() (which needs to be rerun in
every stage) close to console_init(), in the hopes that it will be less
likely overlooked when creating future boards. Also added (an
ineffective) one to the armv4 bootblock implementations for consistency
and in case we want to implement it later.
BUG=None
TEST=Made sure exceptions can fire and get handled correctly in romstage
and ramstage on Nyan and all three stages on Snow.
Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176764
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
console_init() is supposed to be called again in every stage, and we
forgot to do that in romstage. Bad us. (It still worked... kinda.)
BUG=None
TEST=None
Change-Id: I52102d436e42b60c9bcf9183428d4d7afc70698a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176763
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
"Hey guys, I have this awesome idea! How about we put a huge array
filled with 0xa5 into the data segment of our uncompressed romstage
for no particular reason? Give our SPI driver something to do so it
doesn't get too bored, you know?"
Guess it pays off to just hexdump our image and sanity-check it top to
bottom every once in a while...
Also reduces the size because 8K is crazy just to print a bunch of
registers (256 bytes ought to be enough for anybody).
BUG=None
TEST=Triggered an exception, still works as expected (and verified
romstage load size on Nyan is notably smaller now).
Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176762
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is essentially a revert of commit 5a1469d5. The CAR_MIGRATE
mechanism is only useful to migrate variables from a special region
(e.g. cache as RAM) into DRAM-backed CBMEM between different parts of
the romstage (it does not persist into ramstage). Since ARM devices use
SRAM for which there is no reason to become inaccessible in later parts
of the romstage, this mechanism isn't useful for them. Removing it makes
the romstage.ld script much simpler, which has the nice side-effect of
putting the BSS at the end of the memory image (so that cbfstool can
actually figure out that it doesn't need to be part of the ROM image).
BUG=None
TEST=Still boots and the romstage BSS is no longer part of the load
size in the CBFS image.
Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176761
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This sets the SPI4 speed to 33MHz. The bootrom sets it to
408/22=18.5MHz, so this increases the frequency substantially.
However, we still do not achieve much gain from this because there
are still annoying ~500-600ns pauses in between byte transfers.
Copying ramstage takes around 62ms instead of 67ms.
TODO: We should be able to go up to 50MHz, but that does not work
reliably.
BUG=none
BRANCH=none
TEST=tested on nyan, verified frequency with logic analyzer
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I4e56bec24c2a30ef0aa0b279b774c55b3d897410
Reviewed-on: https://chromium-review.googlesource.com/177038
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
The romstage code for rambi uses the mmio way of reading
inputs. However, this is a problem is the GPIOs are set up
as legacy mode. Subsequent warm resets mean the ram_id is
read incorrectly. Ensure the ram_id is read consistently
by keeping the GPIOs for ram_id in mmio mode.
BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted. And rebooted. Now seeing consistent ram_id
values on warm resets.
Change-Id: Ieff98c000be80998854f325754f1e819975d2be5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177230
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The default mode of the SPI controller has prefetching disabled.
That obviously has a performance impact. Enable both caching
and prefetching to make booting faster. This has a significant
impact on streaming data out of SPI.
BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted rambi. Payload loading step went from ~285ms
to ~54ms.
Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177220
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
When a pad is configured for direct IRQ it needs to be in
non-legacy. Additionally, the signal is passed directly to
the APIC by setting the LEVEL and TPE bits in the pad config
register. The APIC can then be configured for level, edge,
and rising/falling.
BUG=chrome-os-partner:24037
BUG=chrome-os-partner:22863
BRANCH=None
TEST=Built and booted with this config. Trackpad is firing interrupts
more than it should, but it appears to be a trackpad firmware
and/or configuration issue.
Change-Id: I00042b2ddba67d6bf23f0e7468d0719196e6f865
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176793
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This patch removes the -ffixed-r8 CFLAG from the coreboot and libpayload
Makefiles. This seems to be a relic from U-Boot, which uses that
register to keep it's global data structure pointer. There's no reason
for us to throw away a perfectly fine register on this already pretty
constrained architecture.
Also removed a config.h inclusion from the Makefile because that should
really be done inside the C files.
BUG=None
TEST=Nyan still boots.
Change-Id: Ia176c0f323c1be07cddf88fa5488788786a27cdf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177110
Reviewed-by: Gabe Black <gabeblack@chromium.org>
We'd been stopping the AVP by calling hlt, but this just puts it into a loop
which it busily executes forever. If the memory the loop is in is replaced,
however, the AVP will race off and do something random. It turns out that it
was writing the early parts of the rom stage into memory on top of the kernel
as it ran, either by coincidence or because it had rebooted and was actually
reloading the stage into memory.
Many thanks to Hung-Te for determining what was being overwritten by what
which helped determine who was doing the overwriting.
BUG=None
TEST=Before this change, booting in normal mode would cause the kernel to
behave strangely, often crashing. With this change, the kernel seems to boot
fine in normal mode.
BRANCH=None
Change-Id: I292c039c28691387e72386d2a9321c29437076ed
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177086
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
These were a bit incomplete and weren't the same as the names in the manual.
The names for the event types were also a little too generic and might have
conflicted with other names. Also changed them from #defines to enums.
BUG=None
TEST=Built and booted on nyan.
BRANCH=None
Change-Id: I8b61e611fb599c0f989bd0ce246cb044464d1bd0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177085
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This voltage is recommended for the CPU when running at 1.8GHz.
BUG=None
TEST=Built and partially booted on the new form factor nyan.
BRANCH=None
Change-Id: I4ae4b16179d1be241119d85986823ad52af4fb70
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176906
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The PMIC used on the older pixel based nyan boards and the newer boards are
different and use a different base offset for their voltage settings. We need
to set them to different values in order to get the correct voltage out.
BUG=None
TEST=With this and other changes, built and booted on old and new nyan boards.
BRANCH=None
Change-Id: Ie37b11802d8c08f07f37c350ceb732f519b69280
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The variable defaults to off because this will very much be the common case.
It's set to y in the nyan config at the moment, though, since the pixel
versions are the most common for now.
BUG=None
TEST=With this and other changes built and booted on old and new nyan boards.
BRANCH=None
Change-Id: Ib42c71e693663ccbea62fbabbc1500a1c7ecef24
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176904
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
We're going to need some logic to decide what to set the PMIC registers to, so
we need to set the registers using code instead of an array. I never really
liked the array way of doing things anyway.
BUG=None
TEST=With this and other changes, built and booted on the new and old nyan
boards.
BRANCH=None
Change-Id: Ice7ee2830b1b24c25ac506ee004574eb861cf1c0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176903
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.
BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours
Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Print a space after a full stop.
BUG=none
TEST=boot tested
BRANCH=none
Change-Id: Ic7d0522ae35079b64ce61956d06ea59843ef9d80
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176756
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
In the process of rewriting cbfstool for ARM and using
a new internal API a regression was introduced that would
silently let you add an ARM payload into an x86 CBFS image
and the other way around. This patch fixes cbfstool to
produce an error in that case again.
BRANCH=none
BUG=none
TEST=emerge-peach_pit with and without my other CL that fixes
the cbfs image type and see it fail without that CL.
Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176711
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
The TPM needs to have the TPM_Startup command sent to it
on all boot paths. The call init_chromeos() in romstage_common()
fulfills this requirement.
BUG=chrome-os-partner:24057
BRANCH=None
TEST=Built and booted. Was able to suspend to ram multiple times
in a row.
Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176803
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Some of the drivers in the kernel were not so happy about
having shared IRQs. Also, sharing IRQs means more code
needs to be run in interrupt context to determine if the IRQ
was meant for a particular device. Fix this.
No more 'mmc1: got irq while runtime suspended' messages.
BUG=chrome-os-partner:24056
BRANCH=None
TEST=Built and booted. Looked at /proc/interrupts and noted no
more sharing between pci devices.
Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176792
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Talking to David Chang, we decided to switch USB_ILIM_SEL
to low to allow the system to negotiate SDP/CDP with the
USB devices for the front USB ports.
BUG=none
BRANCH=none
TEST=boot tested on Beltino
Change-Id: Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176146
Reviewed-by: David Chang <davidchang@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
