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bd533cc109
On nyan boards, the hardware flow control pins for the UART aren't used or connected to anything, but the reset pinmux settings still have them routed out some of the SOC pins. That can break input over the serial console if the pin is pulled in the wrong direction. Also, if the RX line isn't connected to anything, ie if no servo is connected, then we don't want it to float around and potentially draw power through the input pin buffering logic. We add a pull up to it so it will go somewhere in particular if otherwise unattached. This is generally not a great place to put pinmux configuration because it's specific to a particular board but this is shared by everything with a tegra124 in it. It's a good idea to have serial output as soon as possible, though, and the other serial related pinmux settings were probably put here before we really understood the complexities and flexibility of the tegra pinmux. We might want to factor out this part of the serial console config and delegate it to a hook in the mainboard specific code, or just wait until we call bootblock_mainboard_init. BUG=chrome-os-partner:24138 TEST=Built and booted on a peppy based nyan. Before this change serial input was ignored. After this change, serial input was accepted by both the firmware and the kernel. BRANCH=None Change-Id: Ie5428500aa525a600eb1ff4a81b5cc2805d5cc92 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/177637 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> |
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------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.