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d7ddcf262a
Instead of choosing between SDRAM configurations for rev0 nyans and everything else (currently only rev1), we should create a kconfig for each possible config and put them inside a "choice" block. That way we can have an arbitrarily large number of choices without them getting to be hard to manage or accidentally not being mutually exclusive. This also makes the choice of SDRAM config more explicit instead of it being implied by what rev you're compiled for. One tradeoff of this approach is that you need to know which config goes with which rev. Unfortunately we can't decide using the board ID like we can for most other things because the BCT is consumed by code we don't control before any of our own code runs. We default to the slower config for safety's sake, because it will work on both boards, and because it's the right config for the norrin which we were going to transition to soon anyway. Also, we can eliminate the NYAN_IN_A_PIXEL kconfig variable. Alas, we hardly knew ye. BUG=None TEST=Built and booted on both types of nyan. BRANCH=None Change-Id: I9a630189e001e95c740c6741057511bf5939fdbb Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/177580 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> |
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| src | ||
| util | ||
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| README | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.