This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management using the
devicetree infrastructure for the Screebo variant.
BUG=b:430444353
TEST=Able to build and boot google/screebo. Verified touchscreen is
working as expected with this patch.
Change-Id: Ie3456032c232ac92ed7501c08b1c89b0ac274c8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88638
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.
A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.
This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.
TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.
w/o this patch:
```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm UuI5�ፕ�ѥ���������ͥ��х�����jm UuI5���ѥ���ፕ�ѥ��m��jm UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG] NCC Frequency bumped to 1.363(GHz)
```
w/ this patch:
```
[NOTE ] coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] Silver Frequency bumped to 1.5168(GHz)
[DEBUG] L3 Frequency bumped to 1.1904(GHz)
```
Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable bootblock compression on the X1p42100 SoC to decrease boot
time by 10-20 ms.
This change helps to reduce the size of the bootblock, allowing it
to be loaded and decompressed faster, which improves overall boot
performance.
TEST=Able to build and boot google/quenbi.
Change-Id: I81cdbec4a05c8abacae39ff208cc0f7469206161
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88626
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to use CONFIG_DIMM_SPD_SIZE to determine the
amount of data to read from the SPD, then override that value.
Clean up the mess and simply set the SPD length fror the spd_block
struct to CONFIG_DIMM_SPD_SIZE.
Change-Id: Ifec6cf1f6d7c931131460ea72440aa236590d0b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88523
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code was copied for Meteorlake.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82733
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75284
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This change allows flag to be override via devicetree,
instead of relying on the default value in alc711_slave.
It helps fix the missing event issue when plugging or
unplugging the 3.5mm headphone jack.
BUG=b:417133565, b:420516709
TEST=Verified build and boot with ALC721 and ALC722.
Headphone path switches successfully via audio jack event.
Confirmed SSDT dump at PCI0.HDAS.SNDW.
Package (0x02)
{
"mipi-sdw-simplified-clockstopprepare-sm-supported",
Zero
},
Change-Id: I975ed83e8614bd88861f115ffeea7c2450e6a432
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Allow overriding the default value (true) via devicetree configuration.
If disable_clkstop_sm_support is set in the devicetree,
the corresponding field in alc711_slave is set to false.
BUG=b:417133565, b:420516709
TEST=Verified build and boot with ALC721 and ALC722.
Headphone path switches successfully via audio jack event.
Confirmed SSDT dump at PCI0.HDAS.SNDW.
Package (0x02)
{
"mipi-sdw-simplified-clockstopprepare-sm-supported",
Zero
},
Change-Id: If958cd0c2136e4dd3f60cb9203d9394913d3f66e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88586
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since MT8189G does not support APU, the LDO_VSRAM_OTHERS and BUCK_VCORE
regulators for the APU power domain can be turned off. Disabling these
power supplies reduces overall system power consumption by about 1mW.
BUG=b:420874944,b:421989583,b:423081787
BRANCH=none
TEST=Verified by measuring system current in S3 state before and after
disabling APU power.
Signed-off-by: Niklaus Liu <niklausi.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4e4eeb575327b554f5837bfc0f6a464ff7a1e228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Include `stdint.h` in `cpu_id.h` to ensure `u32` is properly defined.
This resolves build errors when files including `cpu_id.h` cannot find
the definition for `u32`.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If4b41a6eae38470d4d30baeeef50c8b1ebb82033
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88630
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the Kconfig for the Google Ocelot mainboard to
select EC_GOOGLE_CHROMEEC_MEC for the OcelotMCHP and OcelotMCHP4ES
variants.
BUG=b:394208231
TEST=Build Ocelot and verify all variants compiles without any error.
Change-Id: Ie5f776d40029b52a57d82aa9b02b95fbf3905cfd
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88629
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varun Upadhyay <varun.upadhyay@intel.com>
This new variant will support PTL pre-production silicon. The existing
`kinmen` variant will support production silicon.
BUG=b:434847748
TEST=Able to build google/kinmen4es.
Change-Id: If0597c1b63179e46a83286f2d46f958189f627cc
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88622
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Introduce the disable_progress_bar setting in configuration to allow
disabling the memory training progress bar during firmware
initialization.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar
is disabled.
Change-Id: I35e8191df27c0eda634724580514e980bd620136
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now selected at the SoC level and therefore redundant.
Change-Id: Ib6ae94c359d3dac34886147e9078043e4f132f84
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88522
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because we do not want to enable the mipi camera dmic LED
at booting, so pull down the EN_PP2800_WCAM_X.
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).
BUG=b:427962702
TEST= Build and boot to OS, check the LED is off. And
check the mipi camera function works fine.
Change-Id: Ia9ccf3e335ad65c9a8f68fe33226803cc8555228
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88604
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
These will be used in subsequent patches which optimize the reading of
SPDs based on the supported memory type(s).
Change-Id: I8b0d4f37b4b992c42bede25d678cb9afc9db3dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88521
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This patch unifies all the felino variants based on
`BOARD_GOOGLE_MODEL_FELINO` to use the same mainboard part number
`Felino`.
BUG=b:430205874
TEST=Able to build/boot felino
Change-Id: I15a9372e18a910916e9f695d920fc502bf6afa06
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88611
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When bundled fw is NULL the system boot hangs.
Add a judgement to return mismatch when bundled fw is NULL.
BUG=b:434844512
BRANCH=firmware-brox-16080.B
TEST=emerge-brox coreboot
set FW_CONFIG=STORAGE_NVME and DUT can boot into OS
Change-Id: Ibe81e944725b8c387c61451c2e422d57f7aeb8c1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The magic number '1' for VgaInitControl is replaced with the
VGA_INIT_CONTROL_ENABLE macro for improved readability and
maintainability.
This makes the code's intent clearer and aligns with best practices
for using named constants.
The VGA_INIT_CONTROL_ENABLE macro is defined in ux.h along with a
comment to describe its purpose.
TEST=Able to see eSOL while booting google/fatcat.
Change-Id: I27a91030c0aaa52e099869c5870da670d3e28628
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update the verb table to decrease the speaker output level.
BUG=b:404480459
TEST=Build and boot to OS, check test result is pass with
hardware engineer and Realtek.
Change-Id: I4f0544ab220ffdbcb2e61ca2f1d2e0d9ae36b1ce
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88592
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Kaladin support 2 kinds of ELAN touchscreen with different
slave address:
TOP(Touch_IC on Panel): slave address 0x10
DBTS(Touch IC on Daughter BOARD):slave address 0x15
Add FW config to separate ELAN touch screen.
BUG=b:434591789
TEST=build and verified touchscreen work
Change-Id: I3e1c748baf1d392c626ce17f4fcb601ec02ce428
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88585
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit assigns pci_dev_request_bus_master to the .final operation
for both the DSP and HDA device operations to ensure that the bus
master is enabled.
This change ensures correct PCI configuration for DSP and HDA devices,
preventing potential issues with direct memory access operations.
BUG=b:427091370
TEST=Able to build and boot google/fatcat.
w/o this patch
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x02
```
w/ this patch:
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x06
```
Change-Id: Id2480dba08ea8ee7a9219327b8a31f8f9f65410c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management for the Francka
variant.
BUG=b:430444353
TEST=Able to build and boot google/francka. Verified touchscreen is
working as expected with this patch.
Change-Id: I2b6c0cacdc159eaf98279bd57efb81c8454ee580
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports.
This reverts commit 9207621d23.
Change-Id: I453562ab5802c7b9e38b7555415747dd9205aacb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88596
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports
This reverts commit e638a113fa.
Change-Id: I6a6349515f6662d792cf2f069bc847effa33a400
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88595
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After crash data extraction, the records are cleared and reinitialized
to their default values. This is done using watcher interface instead
of BIOS mailbox commands because of low latency and efficiency.
Ref: LNL FAS 733648
BUG= b:None
TEST= iotools mmio_dump 0x9c199d40 0x10 - PMC
0x000000009c199d40: 0xdeadbeef 0xdeadbeef 0xdeadbeef 0xdeadbeef
iotools mmio_dump 0x9c1d0058 0x10 - CPU
0x000000009c1d0058: 0xcafecafe 0xcafecafe 0xcafecafe 0xcafecafe
Initial 8 bytes of header are zeroes - indicating that both header
and crashlog data buffer are cleared
Change-Id: I8a36e091f61833067caf9e9f94ba79149e699d68
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix the ACPI HID and description for Goodix touchpad.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check the touchpad name in evtest.
Change-Id: I44b75841034a2004c62a577e60c630cc0e430fc8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88461
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The I2C2 and I2C3 ports are unused. This patch removes them from overridetree.cb as they are already turned off in chipset_wcl.cb.
BUG=b:434127691
Change-Id: I8c00f7c96915a1a11b848af5ea128900fb5a16db
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88562
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the 2 new Samsung memory support.
DRAM Part Name Vendor Model ID to assign
K3KL6L60GM-MGCT Samsung LPDDR5X 4 (0100)
K3KL8L80EM-MGCU Samsung LPDDR5X 5 (0101)
BUG=b:426427376, b:432169883
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Ib707e2e482dc90bc02d73bd0fcda62630bacf1b5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88449
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch enables QcLib execution for DDR and PMIC initialization.
SHRM and AOP firmware metadata are passed from coreboot to QcLib via
the interface table. On first entry, QcLib authenticates SHRM metadata
through TME and brings SHRM out of reset. Upon re-entry, QcLib forwards
AOP metadata to TME for authentication and brings AOP out of reset.
TEST=Verified QcLib boot (DDR Init, SHRM/AOP authentication & out of
reset flow) on google/bluey.
Change-Id: I4b726d5066ca807bf9d4df70f275e5dd991520cc
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds support to pack aop_meta into CBFS and load QcLib DTB,
SHRM metadata, and AOP metadata. It also populates the QcLib interface
table with these information for firmware authentication and execution.
TEST=Verify presence of AOP metadata file in the CBFS and QcLib
interface table content.
Change-Id: I1a74d9ffbfc10023b0e5610d54218909b18efa01
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable PCIE init for bluey board and update device pci node.
Remove unused pci 4.0 node(WLAN).
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I7ad4a9409ff0465b45b8bb1f3e005bf9f83f2c42
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88535
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I9dd9a5340f28326ebabf12489c11e7f73f2c8d2f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88583
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I8a3cb1b21e712e588f641f70c040a2334faf0031
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The ISH GPIO pads for `ISH_GP_x` (GPP_B04, GPP_B05, GPP_B07, GPP_B08,
GPP_B22, GPP_B23) were previously configured in the generic gpio_table.
This commit moves their configuration to the `ish_enable_pads` and
`ish_disable_pads` structures within `fw_config.c`.
This change ensures that these ISH-specific pads are only configured
when the ISH is enabled, aligning with best practices for power
management and reducing potential conflicts when ISH is not in use.
BUG=b:396557201
TEST=Able to build and boot google/fatcat w/ ISH enable and/or disable.
Change-Id: I4ef896d220fbe5f9c042c4d9df97d32ac238cbc5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The GPP_B06 pin configuration for ISH_GP_2_SNSR_HDR is never required
for the Panther Lake SoC/ISH. This commit removes the obsolete entry
from the GPIO table, streamlining the configuration.
BUG=b:396557201
TEST=Able to build and boot google/fatcat.
Change-Id: I3f38c52a305d14e21c7fcf2dfb943133ae4a7e45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
We use internal bypass for kaladin, so remove the external bypass settings
BUG=b:432378989
TEST=Flash and boot up kaladin, test that DUT can enter S0ix
Change-Id: I84207a21f15de2df813387e16065688f409b2523
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
GPP_F18 is the correct wake on touch GPIO, which overrides GPP_DW0_18.
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST=Touchpad works on ocelot RVP
Change-Id: I4ea9c36a371d69f829ba64bfeb35ab9afccf1e06
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88540
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board came virtually rebranded from a specific German OEM called
Wortmann AG and was identified as "TERRA_PC/H81M-D2W" model: 1009381.
It however ships a GIGABYTE GA-H81M-D2W rev 1.0 branded motherboard
which is extremely similar to a Retail GIGABYTE GA-H81M-D2V rev 1.0.
The only obvious differences are the onboard video outputs, its serial
connectivity and total abscence of it on the GIGABYTE support website.
- GA-H81M-D2W
DVI-D + DVI-I + serial port header on motherboard
- GA-H81M-D2V
DVI-D + VGA + DB9 serial port connector on backplate
Mainboard: GIGABYTE GA-H81M-D2W rev 1.0
Pure autoport (initial commit) doesn't boot, second patch brings up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, PCIe fixes enabling onboard LAN and other PCIe slots
and some IT8625E superio code from a other coreboot port made most
ITE8620E superio related functions work, especially WDT otherwise this
board resets every couple of seconds! Autoport did log hda codec / pins
but it didn't include them in the hda_verb.c, so I added them manually
which also fixes pcspkr (beep codes, not soundcard connected).
Flash instructions:
Internal flashing using flashrom works on OEM and when running coreboot
using the following command: flashrom -p internal -c "MX25L6473F" -w ROM
An external flasher ch341a_spi (3.3v mod) used with a SOIC 8 pomona
probe to recover the MX25L6473F in situ also works without issues. Only
the power of the USB programmer was used, and the board's main PSU was
disconnected during external flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- Broadwell mrc.bin (tidus)
- Haswell mrc.bin (peppy used for all mrc.bin noted testing)
- Haswell NRI
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- DVI-D & DVI-I (VGA) all work during POST, BOOT and OS
- Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
- RAM single and dual slot 2GB/4GB/8GB mixed DDR3 DIMMS max 6, 8, 16GB
(NRI & mrc.bin)
0/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
0/2: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
0/2: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
(NRI single DIMM won't mix with others)
0/2: 8GB DDR3-1600 - SK Hynix HMT41GU6MFR8C-PB (2023-W20)
(ECC UDIMM, mrc.bin only, see NRI note below)
0&2: 4GB DDR3-1600 ECC - Kingston 9965432-051.A00LF (2013-W19)
0&2: 8GB DDR3-1866 ECC - Micron 18JSF1G72AZ-1G9E1 (2013-W29)
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- MS Windows 10 / 11
- Audio Outputs both DVI > HDMI, Headphone, Line Out (left&right chan.)
- Audio Input Line In (back)
- pcspkr
- USB2/3 all Intel ports
- SATA 4 ports
- PCIe slots (16x 5GT/s & both 1x 5GT/s)
- iGPU (plus dGPU as in dual GPU work both with mrc.bin / Haswell NRI)
- dGPU (nVidia GeForce GT640-2GD3 2.5GT/s / Radeon HD7770-1GB 5GT/s)
- Realtek RTL8111F onboard Gb LAN
- Wake on LAN
- HWM shows both fan speeds and voltages
- PS/2 port (both Keyboard and Mouse with Y splitter cable)
- Serial port header (coreboot console & OS)
- PowerButton (Poweron/Poweroff/Wake)
- ResetButton
- LEDs HDD & POWER (off during suspend)
- Shutdown/Reboot/Suspend
- Strip down the Intel ME/TXE firmware (make menuconfig) see ME note!
- Disabling ME HECI (manually remove from devicetree.cb) see ME note!
- flashrom -p internal -c "MX25L6473F" #read & write
Not tested:
- Audio Inputs Front & Back Microphone Ports
- parallel port header
- USBDEBUG
- VBIOS
Not working:
- Disable Intel ME PCI interface (make menuconfig)
- USB2/3 all VIA VL805 backpanel ports
FD layout note:
The original OEM firmware ships a BIOS region that seem to use the
whole firmware:
00000000:00000fff fd
00000000:007fffff bios
00001000:001fffff me
Although coreboot works fine with this flash descriptor layout it is
mandatory to flash a complete image! Replacing only a specific region
like the BIOS region when relying on --ifd will confuse flashrom and
trash the flash chip's contents! As a temporary measure one can use
--layout to flash a specific region using the following layout:
00000000:00000fff fd
00001000:001fffff me
00200000:007fffff bios
Permanently changing the flash descriptor layout to look like this will
solve flashing specific regions and remains a valid option since it
cannot break GIGABYTE its DualBIOS feature since its absent.
NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
ECC UDIMMs currently do not work on this board because NRI does
not check whether the board / chipset support ECC. This results
in RCVET failures for the ECC bytelane (byte 8). Eventually this
will be fixed in NRI. Haswell mrc.bin works as expected.
ME note:
Neutering the ME will let the system still function correctly, unless
you include EFFS and FCRS partitions addressed by ME_CLEANER_ARGS:
"-S --whitelist EFFS,FCRS"
Failing to supply these ME partitions will cripple superio functions as
in serial output (breaks coreboot serial console) and HWM fan and
voltage info goes random nuts while the fan stays at normal speed.
VIA VL805 note:
Without firmware loading (which is still unknown) and enabling it in the
devicetree.cb will give DMAR IOMMU errors therefore disabled by default!
The data.vbt blob was extracted using debugfs from the OEM F5 firmware
which enables both video outputs DVI-D and DVI-I (VGA).
Since this board is not listed on the GIGABYTE website, but it works
with the Retail GA-H81M-D2V F6 firmware I listed that one instead in the
board_info.txt. However I cannot confirm that this coreboot port also
works for the GA-H81M-D2V, it is good practice to at least check its
gpio values matching this port!
Change-Id: I80dc414a92d115099ec8966841af0cf22d5b1d09
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue
with the 3.5mm headphone jack on the I2S codec AIC not detecting
headphone plug/unplug events. Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
BUG=b:434208278
TEST=After booting to OS, plug and unplug a headphone to the I2S codec
add-in card, headphone is getting detected.
Change-Id: I1c662ec680d8175be5854c753ea1481d09afb561
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88564
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Becasue of requirement for VCCANA power from MBVR mode to FIVR mode,
so change ICCmax at VCCIN_AUX will be from 25A to 27A due to
internal VR.
BUG=b:417662158
TEST=Build and boot to OS at the rework motherboard and verfied by
power team.
Change-Id: Ie036412c0e435cfce39940de6bab363f9e875f42
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88558
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.
BUG=b:429495479
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.
Change-Id: I0a195c65fe2835f9be66c56fb7129851b3251b90
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88446
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For the latest trulo projects: kaladin,pujjolo,pujjocent,
the original comment was too brief and led to some misunderstanding.
In the past years, only retimer has the SBU muxing function. Or said,
only retimer has Aux Orientation feature. So, 'no retimer' implies
Aux Orientation feature inside the processor is needed.
And now, the modern future PDC also has the Aux Orientation feature.
Not all "no retimer" cases require setting the override bit anymore.
The even numbered bits should be set only when there is no retimer and
the processor's Aux Orientation is still required.
(If set, the SoC inverts the orientation value coming from EC/PDC when
operating in flipped orientation.)
In the referenced issue tracker, the system has 'no retimer' and uses
a 'future PDC'. (The PDC has the Aux Orientation feature.)
Test results (DP + TCSS):
- 'tcss_aux_ori' = 0 + PDC sends orientation detected value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends 'original' value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends orientation detected value -> FAIL
(Fail means only display one side.)
This patch updates the comment to more accurately describe the expected
usage and avoid future confusion.
Refer doc#:
646929 TWL PDG
734752 TCSS Cookbook (MTL Backward/MTL/PTL/WCL)
627270 TWL Bios Spec
758766 MTL Bios Spec
766031 MTL PDG
BUG=b:4292672
BRANCH=none
TEST=Update coreboot device tree with different tcss_aux_ori value and
test the DP connection via TCSS on 2 orientations.
Change-Id: I3281110e522c53a35abf30fd1c372bb5ca18c10d
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88482
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
