This commit modifies the Fatcat mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.
This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/fatcat to UI without valid Audio configuration.
Change-Id: I7d1fa07978725129c2651f258894f3590e0a69eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
The cache buffer is expected to be aligned to CONFIG_CBFS_CACHE_ALIGN by
the mem_pool_alloc function.
Change-Id: I153a4de5ae2b8549288946d0773009d586d5c65c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88299
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures Interrupt, Enable and Reset pins for FPS.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option to enable/disable ISH.Removed the
copies and redundant ISH pins from GPIO.c
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I02bfa6b90b1c37a1d69d094804b4153e191a29af
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88329
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.
BUG=b:427091370
TEST=Boot beep verification is possible using google/fatcat.
Change-Id: Ibeca991b9e855792df48073d2138b9c7ec130c41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88350
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Boot Profile for use with the IFWI Boot Flow. The selected profile
should be equal to or higher than the one configured in IFWI.
No Profile
Since its inception, coreboot has ignored the Boot Flow designed by
Intel; this only uses an IBB and OBB. Neither are measured or verified
and mapped without assistance.
Legacy
Profile 0 is for platforms that do not wish to enable Boot Guard boot
block verification or measurement enforcement.
Verified
Profile 1 is strict Verification enforcement. It prevents unverified
BIOS components from running.
Verified and Measured
Boot Guard Profile 2 is strict Verification and Measurement
enforcement; this prevents unverified BIOS components from running.
Upon manufacturing completion, this value is burned into an FPF
and is permanent. This setting is only configurable when OEM signing
is enabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83d2fd134e1a893766f625fe2e2ddd81d48f9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When parsing the string, if it doesn't end with 0 or \n, get_line_as_int
returns -1, but wasn't freeing the buffer. Also if we got an empty
string with just null termination, that byte would also cause a leak, so
move the second free() to the bottom. It's always fine to free a null
pointer if the allocation failed.
BUG=CID 1419489
Change-Id: Ibb3a7544ec8c46820b6e47b6fd4bbe5cabafe1a8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88335
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When returning from cbmem_console_snapshot() because of a corrupted
console structure, the memory that was just allocated was not being
freed as it "should be".
BUG=CID 1419477
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I85370fb49c9ef9a00cd2ea516fa80c9e152c9b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This documents that if the fw_cfg table was improperly configured by
QEMU, the fw_cfg_smbios_init() function would leak memory. We could
add a check to verify that this doesn't happen, but honestly that seems
like overkill. This just documents the issue in case this code is
copied for use elsewhere.
BUG=CIDs 1405799, 1405791, 1405792, 1405796, 1405797
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f253194dae52897633ab5d96bb8c2964b8365d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the CRFP device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the CRFP device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.
BUG=b:428793056
TEST=Boot the board and make sure the FPMCU was booted once
(e.g. examine FPMCU console logs)
TEST=Dump SSDT on kinmen
Scope (\_SB.PCI0.SPI0)
{
Device (CRFP)
{
...
...
PowerResource (PR00, 0x00, 0x0000)
{
Method (_STA, 0, Serialized) // _STA: Status
{
0x5D = \_SB.PCI0.GTXS /* External reference */
Local0
If (!Local0)
{
Return (Zero)
}
0x27 = \_SB.PCI0.GTXS /* External reference */
Local0
Local0 ^= One
If (Local0)
{
Return (Zero)
}
Return (One)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
Local0 = _STA ()
If ((Local0 == One))
{
Return (Zero)
}
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.STXS (0x5D)
Sleep (0x03)
\_SB.PCI0.STXS (0x27)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.CTXS (0x5D)
}
}
}
}
Change-Id: Ia3054c61dfab185d124b3aae8df9e80aa6afc71a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88338
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf
BUG=b:429335394
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.
Change-Id: Ic1c4bea599db23d5bc760bb7a54a2581cb293ce3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88284
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not use the board_id-feature hence the code can be
removed.
Change-Id: I18c67580d4611b4c53248315937277bed53bd1ea
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard does not have an embedded controller (EC), therefore
remove the code for it.
Change-Id: Ib37b3cc257f7ac4af6a6505a3e43c9e5275fcd3f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88262
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard will just have a single VBT in cbfs which will be named
as the default name is (vbt.bin). There is no need to chose between
different configurations for the VBT selection. Therefore, remove the
corresponding code.
Change-Id: Ia72e8bae23c15476c362e456dc8358bec3b102a5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard is not going to use Type-C subsystem. Therefore, disable
and remove the config data for it.
Change-Id: I2d9e53bf63b41811040f84cfe9dedf275f1059e4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88260
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens boards store their memory configuration data (SPD) in a field
inside the HWInfo block (which itself is located in CBFS). This patch
removes all *spd.hex-files and uses HWInfo instead for the SPD data
source. In addition, the memory data swizzling is updated to reflect
the board wiring so that DRAM can work properly.
Change-Id: I63d6e7c4543b7d99a4b1815c8ee81efcb6a87b94
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
While reviewing CB:87192 that deals with this option on another
mainboard, it was found that northbridge/intel/sandybridge
actually could not handle this option (present on Ivy Bridge
only anyway) properly. It would only factor 544MB into memory
calculations while telling IGD it can use 1024MB.
Until a fix can be implemented there, remove this option from
Ivy Bridge mainboards.
Change-Id: I0c87c52ef050cca54e050de3d41603c4ab29740b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88294
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Values here above 512M are:
1. Inconsistent with Intel IVB datasheet vol.2, document #326765;
2. Apparently not properly supported by nb/intel/sandybridge.
Take them out until a fix can be implemented.
Change-Id: I6183f447af2816d00c9f6d78329113cd9c584191
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88293
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is missing option values for 256MB and up.
Make complete by referencing asus/p8x7x-series and Intel IVB
datasheet vol.2, document #326765.
Intel datasheet lists an additional 1GB option for Ivy Bridge
CPUs, but since nb/intel/sandybridge/northbridge.c has been
found to not handle this setting properly when doing memory
calculations, a fix is needed there before it can be included.
It was not an option for Sandy Bridge anyway.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Id89290a673b0e5dbc72c11c097aeb70d410adeab
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Recent development of the "pro_6300" variant fixed the 4th sata port,
using "register sata_port_map" = "0x17" in "overridetree.cb" the same
is valid for the following 2 variants:
- compaq_8300_elite_sff
- compaq_8200_elite_sff
BUG=581#note-22
TEST=grub2 output & dmesg output
p4
�����������������������������������������
� Boot Menu �
�����������������������������������������
Device Path :
Select a Boot Device PciRoot(0x0)/Pci(0x1F,
0x2)/Sata(0x4,0xFFFF,0
UEFI Shell x0)
USB Device
SATA: hp DVD A DH16ABSH
dmesg | grep SATA | grep link
[ 4.994271] ata1: SATA link down (SStatus 0 SControl 300)
[ 5.304068] ata2: SATA link down (SStatus 0 SControl 300)
[ 5.616102] ata3: SATA link down (SStatus 0 SControl 300)
[ 5.920122] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
Change-Id: Idcef5854e1e97380bec12374411ddfdb50395c29
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SPI NOR clock from 26MHz to 52MHz to improve boot time.
BUG=b:379008996
BRANCH=none
TEST=Verified clock rate via oscilloscope, and measure boot time with
cbmem
(previous) Total Time: 800,539
(now) Total Time: 739,292
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe3df8200417fa9a8292bfd3c29339b7d125e3c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add 3 new timestamps for measuring the time to setup pvmfw in
depthcharge. First indicate when the setup has started. Second when the
comm with GSC has finished and third when the setup is complete.
BUG=b:429115233
BUG=b:359340876
TEST=build rauru
Change-Id: I0e0d069ae85997d3e4c02f257cd801e7b6787762
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There can be cases where it is needed to provide the SPD data in a
different way than an EEPROM or CBFS file. This patch adds a third
method where the SPD data can be provided in a memory buffer for
memory-down configurations. Where this memory buffer comes from
and how SPD data is filled in is up to the mainboard code.
To use this new method set 'spd_data.in_mem' to 'true' and provide a
pointer to the SPD data in memory via 'spd_data.ptr' where
'spd_data.len' holds the length of the SPD data in that buffer.
This feature is useful for Siemens mainboards where the SPD data is part
of a larger configuration block called 'HWInfo block'. Though this block
itself do reside in CBFS, the SPD data cannot simply be indexed into
(like with the cbfs_index). Instead, the hwinfo-lib is used to get
dedicated fields from that block, this includes the SPD data, too. With
this patch the SPD data can be retrieved from HWInfo block and passed as
a buffer to the memory initialization code.
Change-Id: I2bd4970967cfe81bba96d8e2b2fd3a0bb85430c4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88258
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 712dfb3761.
printf formats fixed to use PRI* macros instead of raw values.
BUG=b:391874512
TEST=cbmem -l; cbmem -x; cbmem -r 434f4e53; cbmem -t; cbmem -c \
On both x86 (Brya) and ARM64 (Corsola)
Change-Id: Iba6e3af080fe10c4a55adfcaee9c373a2cce1378
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88292
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During finalize_load(), cpu/x86/mtrr/earlymtrr.c:postcar_mtrr is signaled
to be loaded as reloc_params, e.g. with its cache flushed.
Add a comment line to specify the relationship to improve the readability.
I didn't see code to set up parameter at first time.
So, I just guess that adding a comment would be helpful. :)
Change-Id: Ic7d3f9cf514ce5a8efc2af9e78992cb39a91e537
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86866
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
When battery is not present, reduce power limits to below 45W,
avoid inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the powerlimit to 38w.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built(emerge-nissa coreboot chromeos-bootimage) and push ap firmware to dut.
2、Connect 15W machine without battery to 45W adapter and check if it starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38 watts.
Change-Id: I72429052f5b3d25e56076176728498357a298cdd
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88282
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Do not attempt to use the VBOOT pkgconfig file when it doesn't exist.
Change-Id: I9633fc7fb060b1d00fddfd938ff2956c03b24274
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88319
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It makes it easier to request reviews on patches or report bugs.
Change-Id: Icaefa00c866ec6600637f67e7906f523b36348cb
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88276
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Rephrase some items
- Add additional code examples
- Add additional sections
- Update documentation to the current state of the codebase.
Change-Id: I6e4cc244edf6cc860cc66165173f134a30a81589
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Linux (bzImage) payloads used to be totally not compressed with
cbfstool. However, only bzImage is already compressed and initrd is
usually compressed, but the trampoline, parameter, and kernel command
line should be compressible.
Now cbfstool can copy segments instead when compression fails, so
compression for Linux payloads (including LinuxBoot) could be enabled
for compressible components.
TEST=With LZMA, parameter is compressed from 0x1000 to 0x4c,
trampoline is compressed from 0x171 to 0x14b, kernel command line
is not compressed for being too short (0x22), initrd is not
compressed for being already compressed.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8af3c904de55910a1298673d8ec2925a317bcff5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When compression fails (usually due to larger result), we could retry
with memcpy() as in cbfs-mkpayload.c, instead of stopping immediately.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Id8b2cffef3832c4bad49bd722c9a5133735f61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87934
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The IOT version of FSP is inconsistent at resuming from S3,
so switch to the client version.
Change-Id: Ifadfebf53e20bc82e6272ea28e5bc443b9829545
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Replace the existing TWL FSP headers, which were copied from ADL-N,
with the actual TWL headers.
TEST=starlabs byte_twl passes abuild w/o using IOT FSP.
Change-Id: I5c2836e81dee47dee73b14ce02f7bb8d0e846135
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This algorithm minimises the per-channel, per-lane digital COMP offsets
by adjusting the global COMP offset accordingly. The purpose of this is
not fully known, but it is likely to prevent saturation of per-channel,
per-lane registers during subsequent training steps, which NRI does not
implement yet. Some of the COMP offset functions are generic since they
are also used in said training steps.
Tested on Asrock B85M Pro4, still boots to Arch Linux.
Change-Id: Idb03c6c5ed85a522ff1b55905f522211d1472bd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87833
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Builds using SBOM were failing in the release because we don't have a
git tree to get information from. We can't assume that the coreboot
source will always be in a git tree, so it needs to be updated. This
updates build.h to contain all the data that the SBOM wants and changes
the SBOM makefile to get its information from build.h which can generate
the required data in a number of different ways.
Change-Id: I59fba349d95cb0dcff7a31d335f4acb4f11c89c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit updates the platform reporting logic to recognize the
Wildcat Lake SoC CPU ID.
Key changes:
- Add CPUID_WILDCATLAKE_A0 to the list of recognized CPU IDs in
the platform reporting module.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I8c9e81446a12ee0a6e18f1ba3f36166652a05f5e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88271
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Enable Realtek ALC722 and ALC1320 soundwire codec for francka.
Refer to the main board schematic(1224A) and
audio board schematic(1106A).
BUG=b:420516709
TEST=Build and boot and check the ssdt dump PCI0.HDAS.SNDW.
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW00)
Name (_ADR, 0x000030025D072201) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW20)
Name (_ADR, 0x000230025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW30)
Name (_ADR, 0x000330025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Change-Id: I542d94fd792272d3b7d75538671ba2f59c331a1e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Because of the internal misunderstanding, so now correct the right fw
config of wifi SAR id number from 18 to 21 to 17 to 20.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check coreboot log to check the wifi SAR table could work fine.
Change-Id: Ib006996fb8887a36feb5dfe71baef58fa74c35f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to a recent acpica version upgrade, the acpica tool is now
failing to download due to an incorrect url. This commit aims to
fix the issue by updating the iasl base url to match the upgraded
version.
Change-Id: I7eddff2d17587f5d90295928800c10068c8cf281
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.
The result is that the power LED toggles on/off every second.
TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.
Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
