- cleanup the w83627hf header, and function names
- rename power_led to w83627hf_power_led
- rename w832627hf_power_after_power_fail to w83627hf_power_after_power_fail
- smbus_read_block != smbus_read_byte
- Update build_opt_tble to handle checksum entries
----------------------------------------------------------------------
src/ram/ramtest.inc{Add movnti ... }
src/southbridge/intel/82801ca/{sync the directory}
src/southbridge/intel/82870/{sync the directory}
src/southbridge/via/vt8231/southgbridge.c
- Transform intel_conf_xxx into pcibios_xxxx
src/southbridge/via/v82c686/southgbridge.c
- Transform intel_conf_xxx into pcibios_xxxx
src/winbond/w83627hf/Config
- Enable the hardware monitor
- Add support for turning on the power_led
util/config/NLBConfig.py
- Add support for object <something>.c
- Add support for object <something>.S
- recode how the list of source files is built up.
util/lb-dump/dump_lb_table.c
- Fix the memory size abreviations
- Support for remember our compile time environment
- Simple and always correct version of compute_ip_checksum
- Improve message strings in crt0.base
- Initial support for > 2G ram.
- Sizeram now returns a list of valid ranges of ram
- pci resource allocation now starts at 0xC0000000
- Update sizeram for every northbridge
- Misc cleanups.
Not really needed, but in the BIOS paranoia is a healthy frame of mind.
Added some debug prints to newpci.c
Fixed sbc710 Config to ensure that com1 and com2 are enabled
(input still does not work)
Changed
extern struct ... *all_superio in hardwaremain.c to
extern struct ... all_superio[] to avoid gcc dereferencing the pointer
(when did THIS C behavior change go in?)
- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
with addresses that are not cached so writing to ram does not work.
Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
the 16bit entry code in SMP.
- A small number of fixes for warnings
- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h. loglevel.h is safe for both
the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
I now allow the other SMP processors to report their existence.
I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates. The code isn't done but it now works on more
than one board at a time.
- More cacheram work. Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
This also includes a bunch of my pending work including
- Updated serial code so we can compile in different serial port speeds
- Updates to the build system so that:
- Makefile.settings holds all of the settings of the config variables
- ldoptions and cpuflags are generated automatically with perl scripts
- src/config/Config holds all of the architecture neutral make file settings
- Initial work on the P4 including how to use cache as ram
- Update to the ioapic code for the P4 because it delivers irqs on the system
bus instead of an out of band bus
- Updated version of printf that doesn't need an intermediate buffer
- logbuf_subr now handles the case when we want to use a log buffer
- video_subr handles the preliminary code for writing to a video device.
- Pending changes for the L440GX are merged in as well (hopefully I haven't
messed then up since they were written).
newpci.c has some new functions. asus config is fixed for i386 stuff.
NLBconfig has a new command (nsuperio) and will take arch, mainboard, or
target as the first command. sis 950 superio has changes for the new
superio model
First, grow heap size in src/arch/i386/config/ldscript.base for DoC
Minor include fixes
Fixes to cua -- but it's now broken, won't find IDE
Minor fix to util/config/NLBConfig.py: for docipl, use CFLAGS
Added files so that CUA works with config tool.
