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Add IDE_SECONDARY to config for pcm-5823

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piix4e fixes from John Usher
Fix to Config for 5530
Fix the glitchy fdc37b72x superio which glitches badly on baud rate changes
This commit is contained in:
Ronald G. Minnich 2002-10-21 14:28:55 +00:00
commit d0bec9e108
4 changed files with 23 additions and 14 deletions
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2
src/mainboard/advantech/pcm-5823/Config
View file

@ -48,7 +48,7 @@ option CS5530_INTC=11
option CS5530_INTD=15
option CS5530_PRIMARY_IDE=1
#option CS5530_SECONDARY_IDE=1
option CS5530_SECONDARY_IDE=1
########################################################################

24
src/southbridge/intel/piix4e/southbridge.c
View file

@ -8,6 +8,8 @@ southbridge_fixup()
{
#if (CONFIG_LINUXBIOS_ENABLE_IDE == 1)
struct pci_dev *pcidev;
struct pci_dev *pcidevdebug;
int i;
printk_info( "Enabling IDE...");
@ -16,22 +18,24 @@ southbridge_fixup()
if (! pcidev) {
printk_err("Can't find piix4e\n");
} else {
unsigned char c;
unsigned short c;
pci_read_config_word(pcidev, 0x41, &c);
c |= 0x80;
pci_write_config_word(pcidev, 0x41, &c);
pci_read_config_word(pcidev, 0x43, &c);
c |= 0x80;
pci_write_config_word(pcidev, 0x43, &c);
pci_read_config_word(pcidev, 0x40, &c);
c |= 0x8000;
printk_info( "0x40 = 0x%04x\n", c);
pci_write_config_word(pcidev, 0x40, c);
pci_read_config_word(pcidev, 0x42, &c);
c |= 0x8000;
printk_info( "0x42 = 0x%04x\n", c);
pci_write_config_word(pcidev, 0x42, c);
printk_info("Enabled IDE for channels 1 and 2\n");
#if (CONFIG_LINUXBIOS_LEGACY_IDE == 1)
printk_info("Enabling Legacy IDE\n");
pci_read_config_word(pcidev, 4, &c);
c |= 1;
pci_write_config_word(pcidev, 4, &c);
pci_read_config_word(pcidev, 4, &c);
printk_info("Word at 4 is now 0x%x\n", c);
pci_write_config_word(pcidev, 4, c);
pci_read_config_word(pcidev, 4, c);
printk_info("Word at 4 is now 0x%04x\n", c);
#endif
}

1
src/southbridge/nsc/cs5530/Config
View file

@ -2,6 +2,7 @@
# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
# Config file for the National Semiconductor CS5530 southbridge
# a.k.a. companion chip
option CONFIG_UDELAY_TSC=1
object southbridge.o

8
src/superio/SMC/fdc37b72x/superio.c
View file

@ -187,10 +187,14 @@ static void setup_com(struct superio *sio,
com->base, com->irq);
set_iobase0(sio, com->base);
set_irq0(sio, com->irq);
/* We are initialized so enable the device */
set_enable(sio, 1);
/* Now initialize the com port */
uart_init(com->base, divisor);
/* this piece of crap glitches like crazy when you change
* the baud rate. Delay one second to try to help that.
*/
delay(1);
/* We are initialized so enable the device */
set_enable(sio, 1);
}
}