update HOWTO fos sis.
ipl for 3com905 on dell 350 Working on new superio
This commit is contained in:
Ronald G. Minnich
parent
688d211896
commit
d8582a896b
3 changed files with 159 additions and 105 deletions
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@ -164,6 +164,9 @@ o You now need to figure out where you want to put your build images.
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# We're using disk on chip. Tell it where to find the docipl code
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docipl northsouthbridge/sis/630
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# Tell Config that we're going to use DOC Millenium as the source
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# of the compressed image
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option USE_DOC_MIL
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@ -31,9 +31,55 @@
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#include "ipl.h"
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.org 0xfe000
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.code16
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.org 0xfe00
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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.word gdtptr - EXT(_start) /* offset in segment */
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* invalidate the cache */
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invd
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data32 ljmp $0x10, $.Lprotected
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.Lprotected:
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.code32
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movw $0x18, %bx
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movw %bx, %ds
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movw %bx, %es
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/*
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movw %bx, %fs
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movw %bx, %gs
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*/
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movw %bx, %ss
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// ALL CODE BELOW THIS POINT SUCKS
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dell350_3com905_start:
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cli # Disables the maskable
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# hardware interrupts.
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@ -28,131 +28,136 @@ smc_configuration_state(struct superio *s, int state)
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addr = s->port;
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if (state) {
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outb(0x55, addr);
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return(0);
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}
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else {
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outb(0xAA, addr);
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return(0);
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}
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return(0);
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}
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else {
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outb(0xAA, addr);
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return(0);
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}
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return(-1);
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return(-1);
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}
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static int smc_write(struct superio *s, unsigned char data,
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unsigned char index) {
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unsigned char index)
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{
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unsigned char addr;
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addr = s->port;
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outb(index, addr);
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outb(data, addr+1);
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return(0);
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outb(index, addr);
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outb(data, addr+1);
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return(0);
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}
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static int smc_read(struct superio *s,
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unsigned char index, unsigned char *data) {
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unsigned char index, unsigned char *data)
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{
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unsigned char addr;
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addr = s->port;
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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outb(index, addr);
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*data = inb(addr+1);
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return(0);
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outb(index, addr);
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*data = inb(addr+1);
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return(0);
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}
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static int smc_uart_setup(struct superio *s,
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int addr1, int irq1,
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int addr2, int irq2) {
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int addr1, int irq1,
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int addr2, int irq2)
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{
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unsigned char addr = s->port;
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int rv;
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unsigned char int1, int2;
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unsigned char data;
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int rv;
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unsigned char int1, int2;
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unsigned char data;
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/*
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* Warning:
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* Board specifc mapping of IRQs here.
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* A configuration mechanism is needed.
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*/
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/*
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* Warning:
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* Board specifc mapping of IRQs here.
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* A configuration mechanism is needed.
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*/
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switch (irq1) {
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case 3: int1 = 1; break;
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case 4: int1 = 2; break;
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case 5: int1 = 3; break;
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case 6: int1 = 4; break;
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case 7: int1 = 5; break;
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case 10: int1 = 6; break;
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case 11: int1 = 8; break;
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default: int1 = 0;
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}
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switch (irq1) {
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case 3: int1 = 1; break;
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case 4: int1 = 2; break;
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case 5: int1 = 3; break;
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case 6: int1 = 4; break;
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case 7: int1 = 5; break;
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case 10: int1 = 6; break;
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case 11: int1 = 8; break;
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default: int1 = 0;
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}
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switch (irq2) {
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case 3: int2 = 1; break;
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case 4: int2 = 2; break;
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case 5: int2 = 3; break;
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case 6: int2 = 4; break;
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case 7: int2 = 5; break;
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case 10: int2 = 6; break;
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case 11: int2 = 8; break;
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default: int2 = 0;
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}
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switch (irq2) {
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case 3: int2 = 1; break;
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case 4: int2 = 2; break;
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case 5: int2 = 3; break;
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case 6: int2 = 4; break;
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case 7: int2 = 5; break;
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case 10: int2 = 6; break;
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case 11: int2 = 8; break;
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default: int2 = 0;
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}
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if (int1 == int2) {
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int2 = 0x0f;
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}
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if (int1 == int2) {
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int2 = 0x0f;
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}
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_write(addr, (addr1>>2) & 0xfe, 0x24); if (rv) return(rv);
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rv = smc_write(addr, (addr2>>2) & 0xfe, 0x25); if (rv) return(rv);
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rv = smc_write(addr, (int1<<4) | int2, 0x28); if (rv) return(rv);
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_write(addr, (addr1>>2) & 0xfe, 0x24); if (rv) return(rv);
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rv = smc_write(addr, (addr2>>2) & 0xfe, 0x25); if (rv) return(rv);
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rv = smc_write(addr, (int1<<4) | int2, 0x28); if (rv) return(rv);
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/* Enable INTB output */
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/* Enable INTB output */
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if ((int1==2) || (int2==2)) {
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rv = smc_read(addr, 0x03, &data); if (rv) return(rv);
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rv = smc_write(addr, data | 0x84, 0x03); if (rv) return(rv);
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}
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if ((int1==2) || (int2==2)) {
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rv = smc_read(addr, 0x03, &data); if (rv) return(rv);
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rv = smc_write(addr, data | 0x84, 0x03); if (rv) return(rv);
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}
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rv = smc_configuration_state(addr, 0); return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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static int smc_pp_setup(struct superio *s, int pp_addr, int mode) {
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static int smc_pp_setup(struct superio *s, int pp_addr, int mode)
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{
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unsigned char addr = s->port;
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int rv;
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unsigned char data;
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int rv;
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unsigned char data;
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_read(addr, 0x04, &data); if (rv) return(rv);
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data = (data & (~0x03)) | (mode & 0x03);
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rv = smc_write(addr, data, 0x04); if (rv) return(rv);
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rv = smc_read(addr, 0x04, &data); if (rv) return(rv);
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data = (data & (~0x03)) | (mode & 0x03);
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rv = smc_write(addr, data, 0x04); if (rv) return(rv);
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rv = smc_read(addr, 0x01, &data); if (rv) return(rv);
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data = data & (~0x08);
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rv = smc_write(addr, data, 0x01); if (rv) return(rv);
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rv = smc_read(addr, 0x01, &data); if (rv) return(rv);
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data = data & (~0x08);
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rv = smc_write(addr, data, 0x01); if (rv) return(rv);
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rv = smc_write(addr, (pp_addr>>2) & 0xff, 0x23); if (rv) return(rv);
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rv = smc_write(addr, (pp_addr>>2) & 0xff, 0x23); if (rv) return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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static int smc_validbit(struct superio *s, int valid) {
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static int smc_validbit(struct superio *s, int valid)
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{
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unsigned short addr = s->port;
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int rv;
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unsigned char data;
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int rv;
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unsigned char data;
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_read(addr, 0x00, &data); if (rv) return(rv);
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_read(addr, 0x00, &data); if (rv) return(rv);
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if (valid) {
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data = data | 0x80;
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}
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else {
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data = data & (~0x80);
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}
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if (valid) {
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data = data | 0x80;
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}
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else {
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data = data & (~0x80);
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}
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rv = smc_write(addr, data, 0x00); if (rv) return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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rv = smc_write(addr, data, 0x00); if (rv) return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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static void
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@ -160,27 +165,27 @@ finishup(struct superio *s)
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{
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#if 0
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// fix me later
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enter_pnp(s);
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enter_pnp(s);
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// don't fool with IDE just yet ...
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// don't fool with IDE just yet ...
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// if (s->floppy)
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// enable_floppy(s);
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if (s->com1.enable)
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enable_com(s, PNP_COM1_DEVICE);
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if (s->com2.enable)
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enable_com(s, PNP_COM2_DEVICE);
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if (s->com1.enable)
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enable_com(s, PNP_COM1_DEVICE);
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if (s->com2.enable)
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enable_com(s, PNP_COM2_DEVICE);
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if (s->lpt)
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enable_lpt(s);
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if (s->lpt)
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enable_lpt(s);
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exit_pnp(s);
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exit_pnp(s);
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#endif
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}
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struct superio_control superio_sis_950_control = {
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(void *)0, (void *)0, finishup, 0x2e, "SiS 950"
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(void *)0, (void *)0, finishup, 0x370, "SMC fdc37b807"
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};
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