Add support for fdc37c67x
This commit is contained in:
Ronald G. Minnich
parent
2ccf7ef5a3
commit
a2cd78fb18
3 changed files with 328 additions and 0 deletions
96
src/superio/SMC/fdc37c67x/setup_serial.inc
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96
src/superio/SMC/fdc37c67x/setup_serial.inc
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/*
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* Enable the peripheral devices on the FDC37N769 Super IO chip
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*/
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/*
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* This code is untested but should at least get a serial port working.
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* -Tyson
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*/
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/* The base address is either 0x3F0 or 0x370, depending on config pin */
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#ifndef SMC_BASE
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#error SMC_BASE must be defined as 0x3F0 or 0x370
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#endif
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#if (SMC_BASE == 0x370)
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/* #warning SMC_BASE set to 0x370 */
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#elif (SMC_BASE == 0x3f0)
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/* #warning SMC_BASE set to 0x3f0 */
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#else
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#error SMC_BASE defined as other than 0x3F0 or 0x370
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#endif
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#define SMC_INDEX SMC_BASE
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#define SMC_DATA SMC_BASE+1
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#define SMC_READ(index) \
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mov index, %al ; \
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mov $SMC_BASE, %dx ; \
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outb %al, %dx ; \
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inc %dx ; \
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inb %dx, %al ;
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#define SMC_WRITE(data, index) \
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mov data, %ah ; \
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mov index, %al ; \
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mov $SMC_BASE, %dx ; \
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outb %al, %dx ; \
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inc %dx ; \
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mov %ah, %al ; \
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outb %al, %dx ;
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/* Enter the configuration state */
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mov $0x55, %al
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mov $SMC_BASE, %dx
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outb %al, %dx
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/* Check for Device ID */
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SMC_READ($0x0d)
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cmp %al, 0x04
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je 2f
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mov $0xfe, %al
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outb %al, $0x80
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#if 0
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1: hlt
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jmp 1b
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#endif
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2:
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/* Pin configuration - need to enable IRQ 4 output */
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SMC_WRITE($0xf4, $0x03) ;
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SMC_WRITE($0x88, $0x02) ;
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/* Set address of parallel port */
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#if 0
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SMC_WRITE($0xde, $0x23) ;
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#endif
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/* Set address of serial port 0 */
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SMC_WRITE($0xfe, $0x24) ;
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/* Set address of serial port 1 */
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SMC_WRITE($0xbe, $0x25) ;
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/* Set IRQs of serial ports */
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SMC_WRITE($0x21, $0x28) ;
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/* Set valid bit */
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SMC_READ($0x00)
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or $0x80, %al
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SMC_WRITE(%al, $0x00)
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/* Exit the configuration state */
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mov $0xAA, %al
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mov $SMC_BASE, %dx
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outb %al, %dx
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215
src/superio/SMC/fdc37c67x/superio.c
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215
src/superio/SMC/fdc37c67x/superio.c
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#include <subr.h>
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#include <cpu/p5/io.h>
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#define PNP_COM1_DEVICE 0x03
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#define PNP_COM2_DEVICE 0x03
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/*
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* This file is for setting up the SMC Super IO chip.
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*
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* This file contains some hard coded mappings for IRQs which may
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* work for most boards but is really board specific. A
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* configuration mechanism is needed.
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*
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* I have only implemented the UART features that I needed at
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* the time plus enableing EPP mode to get interrupts that can
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* be shared. Other features for floppies and parallel ports
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* can be added by others as needed.
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*
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* -Tyson Sawyer tyson@rwii.com
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*
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* Sharing interrupts between two SMC chips doesn't work for me. -tds
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*/
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static int smc_configuration_state(int addr, int state) {
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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if (state) {
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outb(0x55, addr);
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return(0);
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}
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else {
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outb(0xAA, addr);
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return(0);
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}
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return(-1);
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}
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static int smc_write(int addr, unsigned char data, unsigned char index) {
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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outb(index, addr);
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outb(data, addr+1);
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return(0);
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}
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static int smc_read(int addr, unsigned char index, unsigned char *data) {
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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outb(index, addr);
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*data = inb(addr+1);
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return(0);
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}
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int smc_uart_setup(int addr,
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int addr1, int irq1,
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int addr2, int irq2) {
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int rv;
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unsigned char int1, int2;
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unsigned char data;
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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/*
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* Warning:
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* Board specifc mapping of IRQs here.
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* A configuration mechanism is needed.
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*/
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switch (irq1) {
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case 3: int1 = 1; break;
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case 4: int1 = 2; break;
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case 5: int1 = 3; break;
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case 6: int1 = 4; break;
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case 7: int1 = 5; break;
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case 10: int1 = 6; break;
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case 11: int1 = 8; break;
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default: int1 = 0;
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}
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switch (irq2) {
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case 3: int2 = 1; break;
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case 4: int2 = 2; break;
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case 5: int2 = 3; break;
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case 6: int2 = 4; break;
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case 7: int2 = 5; break;
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case 10: int2 = 6; break;
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case 11: int2 = 8; break;
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default: int2 = 0;
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}
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if (int1 == int2) {
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int2 = 0x0f;
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}
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_write(addr, (addr1>>2) & 0xfe, 0x24); if (rv) return(rv);
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rv = smc_write(addr, (addr2>>2) & 0xfe, 0x25); if (rv) return(rv);
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rv = smc_write(addr, (int1<<4) | int2, 0x28); if (rv) return(rv);
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/* Enable INTB output */
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if ((int1==2) || (int2==2)) {
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rv = smc_read(addr, 0x03, &data); if (rv) return(rv);
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rv = smc_write(addr, data | 0x84, 0x03); if (rv) return(rv);
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}
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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int smc_pp_setup(int addr, int pp_addr, int mode) {
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int rv;
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unsigned char data;
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_read(addr, 0x04, &data); if (rv) return(rv);
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data = (data & (~0x03)) | (mode & 0x03);
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rv = smc_write(addr, data, 0x04); if (rv) return(rv);
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rv = smc_read(addr, 0x01, &data); if (rv) return(rv);
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data = data & (~0x08);
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rv = smc_write(addr, data, 0x01); if (rv) return(rv);
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rv = smc_write(addr, (pp_addr>>2) & 0xff, 0x23); if (rv) return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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int smc_validbit(int addr, int valid) {
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int rv;
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unsigned char data;
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if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
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rv = smc_configuration_state(addr, 1); if (rv) return(rv);
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rv = smc_read(addr, 0x00, &data); if (rv) return(rv);
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if (valid) {
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data = data | 0x80;
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}
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else {
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data = data & (~0x80);
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}
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rv = smc_write(addr, data, 0x00); if (rv) return(rv);
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rv = smc_configuration_state(addr, 0); return(rv);
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}
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/*
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* ============== Linux bios standard superio functions ========
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*
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* These functions suck.
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*/
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void
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enter_pnp()
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{
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// unlock it XXX make this a subr at some point
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// outb(0x87, PNPADDR);
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// outb(0x87, PNPADDR);
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}
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void
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exit_pnp()
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{
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/* all done. */
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// select configure control
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// outb(0xaa, PNPADDR);
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}
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#ifdef MUST_ENABLE_FLOPPY
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void enable_floppy()
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{
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/* now set the LDN to floppy LDN */
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// outb(0x7, PNPADDR); /* pick reg. 7 */
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// outb(0x0, PNPDATA); /* LDN 0 to reg. 7 */
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/* now select register 0x30, and set bit 1 in that register */
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// outb(0x30, PNPADDR);
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// outb(0x1, PNPDATA);
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}
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#endif /* MUST_ENABLE_FLOPPY */
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void
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enable_com(int com)
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{
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// unsigned char b;
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/* now set the LDN to com LDN */
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// outb(0x7, PNPADDR); /* pick reg. 7 */
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// outb(com, PNPDATA); /* LDN 0 to reg. 7 */
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/* now select register 0x30, and set bit 1 in that register */
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// outb(0x30, PNPADDR);
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// outb(0x1, PNPDATA);
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}
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void
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final_superio_fixup()
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{
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enter_pnp();
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#ifdef MUST_ENABLE_FLOPPY
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enable_floppy();
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#endif
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enable_com(PNP_COM1_DEVICE);
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enable_com(PNP_COM2_DEVICE);
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exit_pnp();
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}
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17
src/superio/SMC/fdc37c67x/superio.h
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17
src/superio/SMC/fdc37c67x/superio.h
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#ifndef _SMC_SUPER_IO_H_
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#define _SMC_SUPER_IO_H_
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#define SMC_PP_MODE_SPP 0x00
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#define SMC_PP_MODE_EPP_SPP 0x01
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#define SMC_PP_MODE_ECP 0x02
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#define SMC_PP_MODE_EPP_ECP 0x03
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int smc_uart_setup(int smc_addr,
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int addr1, int irq1,
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int addr2, int irq2);
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int smc_pp_setup(int smc_addr, int pp_addr, int mode);
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int smc_validbit(int smc_addr, int valid);
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#endif /* _SMC_SUPER_IO_H_ */
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