Kevin Hester <kevinh@ispiri.com>, fixed irq assignment
This commit is contained in:
Andrew Ip
parent
e288cd8a8a
commit
2783d233d6
6 changed files with 361 additions and 187 deletions
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@ -6,11 +6,12 @@ ldscript cpu/i386/entry32.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/via/vt8231/setup_serial.inc
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mainboardinit superio/via/vt8231/setup_ethernet.inc
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mainboardinit superio/via/vt8231/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit northbridge/via/vt8601/raminit.inc
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mainboardinit southbridge/via/vt8231/ideconfig.inc
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# mainboardinit ram/dump_northbridge.inc
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# mainboardinit ram/ramtest.inc
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# mainboardinit mainboard/via/epia/do_ramtest.inc
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@ -21,18 +22,21 @@ southbridge via/vt8231
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# kevinh - this doesn't build correctly, and I think it is just duplicating
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# the functionality of some of the early setup.
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# superio via/vt8231
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mainboardinit cpu/c3/premtrr.inc
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mainboardinit cpu/p6/earlymtrr.inc
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# The 8231 includes built in Ethernet, however it must be enabled BEFORE
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# the PCI enumeration so that it can be set up.
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option ENABLE_VT8231_LAN=1
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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option FINAL_MAINBOARD_FIXUP=1
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option HAVE_PIRQ_TABLE=1
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option SUPERIO_DEVFN=0x88
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option IOAPIC=1
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option ENABLE_VT8231_LAN=1
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option ENABLE_VT8231_USB=1
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# 021214 aip - irq has problem with native mode, so make sure it is disabled.
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option ENABLE_IDE_NATIVE_MODE=0
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object irq_tables.o
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object mainboard.o
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keyboard pc80
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cpu p5
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cpu p6
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@ -11,19 +11,22 @@ const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0, /* Where the interrupt router lies (dev) */
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0xc20, /* IRQs devoted exclusively to PCI usage */
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0, /* Vendor */
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0, /* Device */
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0, /* Crap (miniport) */
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0, /* Where the interrupt router lies (bus) */
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0x88, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x8231, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x78, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
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{0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
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{0,0x50, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x3, 0},
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{0,0x58, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x4, 0},
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{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
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/* 8231 ethernet */
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{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
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/* 8231 internal */
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{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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/* PCI slot */
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{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
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{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
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{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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}
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};
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@ -5,58 +5,57 @@
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#include <types.h>
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void pci_routing_fixup(void)
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static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
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/*
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Our IDSEL mappings are as follows
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PCI slot is AD31 (device 15) (00:14.0)
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Southbridge is AD28 (device 12) (00:11.0)
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*/
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static void pci_routing_fixup(void)
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{
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struct pci_dev *dev;
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev != NULL) {
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/*
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* initialize PCI interupts - these assignments depend
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* on the PCB routing of PINTA-D
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*/
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/* initialize PCI interupts - these assignments depend
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on the PCB routing of PINTA-D
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PINTA = IRQ11
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PINTB = IRQ5
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PINTC = IRQ10
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PINTD = IRQ12
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*/
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pci_write_config_byte(dev, 0x55, 0xb0);
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pci_write_config_byte(dev, 0x56, 0xa5);
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pci_write_config_byte(dev, 0x57, 0xc0);
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}
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// Standard southbridge components
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printk_info("setting southbridge\n");
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pci_assign_irqs(0, 0x11, southbridgeIrqs);
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// Ethernet built into southbridge
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printk_info("setting ethernet\n");
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pci_assign_irqs(0, 0x12, enetIrqs);
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// PCI slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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}
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void
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ethernet_fixup()
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{
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struct pci_dev *dev;
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u8 byte;
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printk_info("Ethernet fixup\n");
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev != NULL) {
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/* enable lan */
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pci_read_config_byte(dev, 0x51, &byte);
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printk_debug("Get FC 2 in reg. 51 is 0x%x\n", byte);
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byte |= 0x30;
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printk_debug("Set FC 2 in reg. 51 to 0x%x\n", byte);
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pci_write_config_byte(dev, 0x51, byte);
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/* setup interrupt */
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pci_read_config_byte(dev, 0x4d, &byte);
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printk_debug("Get IRQ Control in reg. 4d is 0x%x\n", byte);
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byte |= 0x20;
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printk_debug("Set IRQ Control in reg. 4d to 0x%x\n", byte);
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pci_write_config_byte(dev, 0x4d, byte);
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/* setup PINTA */
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pci_read_config_byte(dev, 0x55, &byte);
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printk_debug("Get IRQ Control in reg. 55 is 0x%x\n", byte);
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byte = 0x50;
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printk_debug("Set IRQ Control in reg. 55 to 0x%x\n", byte);
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pci_write_config_byte(dev, 0x55, byte);
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}
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}
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void
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mainboard_fixup()
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{
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printk_info("Mainboard fixup\n");
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southbridge_fixup();
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pci_routing_fixup();
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}
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void
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@ -68,7 +67,6 @@ final_southbridge_fixup()
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keyboard_on();
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southbridge_fixup();
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pci_routing_fixup();
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ethernet_fixup();
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}
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void
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9
src/southbridge/via/vt8231/ideconfig.inc
Normal file
9
src/southbridge/via/vt8231/ideconfig.inc
Normal file
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@ -0,0 +1,9 @@
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config_ide:
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// This early setup switches IDE into compatibility mode before PCI gets
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// a chance to assign I/Os
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movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// movb $0x09, %dl
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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@ -1,101 +1,208 @@
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#include <pci.h>
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#include <pc80/keyboard.h>
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#include <pc80/mc146818rtc.h>
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#include <printk.h>
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#include <pci_ids.h>
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#include <arch/io.h>
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void keyboard_on()
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// #define IDE_NATIVE_MODE 1
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void usb_on()
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{
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volatile unsigned char regval;
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struct pci_dev *dev;
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unsigned char regval;
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printk_debug("keyboard_on\n");
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regval = 0xcf;
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev) {
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pci_write_config_byte(dev, 0x51, regval);
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/* Base 8231 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231, 0);
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/* USB controller 1 */
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struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_82C586_2, 0);
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/* USB controller 2 */
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struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_82C586_2, \
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dev2);
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#if ENABLE_VT8231_USB
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/* enable USB1 */
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if(dev2) {
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pci_write_config_byte(dev2, 0x3c, 0x05);
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pci_write_config_byte(dev2, 0x04, 0x07);
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}
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval &= ~(0x10);
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pci_write_config_byte(dev0, 0x50, regval);
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}
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/* enable USB2 */
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if(dev3) {
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pci_write_config_byte(dev3, 0x3c, 0x05);
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pci_write_config_byte(dev3, 0x04, 0x07);
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}
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval &= ~(0x20);
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pci_write_config_byte(dev0, 0x50, regval);
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}
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#else
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/* disable USB1 */
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
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if (dev) {
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pci_write_config_byte(dev, 0x3c, 0x00);
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}
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if (dev) {
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pci_write_config_byte(dev, 0x04, 0x00);
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if(dev2) {
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pci_write_config_byte(dev2, 0x3c, 0x00);
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pci_write_config_byte(dev2, 0x04, 0x00);
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}
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev) {
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pci_read_config_byte(dev, 0x50, ®val);
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regval |= 0x10;
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pci_write_config_byte(dev, 0x50, regval);
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval |= 0x10;
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pci_write_config_byte(dev0, 0x50, regval);
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}
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/* disable USB2 */
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, \
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dev);
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if (dev) {
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pci_write_config_byte(dev, 0x3c, 0x00);
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}
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if (dev) {
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pci_write_config_byte(dev, 0x04, 0x00);
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if(dev3) {
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pci_write_config_byte(dev3, 0x3c, 0x00);
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pci_write_config_byte(dev3, 0x04, 0x00);
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}
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev) {
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pci_read_config_byte(dev, 0x50, ®val);
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regval |= 0x20;
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pci_write_config_byte(dev, 0x50, regval);
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval |= 0x20;
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pci_write_config_byte(dev0, 0x50, regval);
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}
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#endif
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}
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void keyboard_on()
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{
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unsigned char regval;
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/* Base 8231 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231, 0);
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/* kevinh/Ispiri - update entire function to use
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new pci_write_config_byte */
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if (dev0) {
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pci_read_config_byte(dev0, 0x51, ®val);
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regval |= 0x0f;
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pci_write_config_byte(dev0, 0x51, regval);
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}
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pc_keyboard_init();
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}
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void nvram_on()
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{
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/* the VIA 8231 South has a very different nvram setup than the piix4e ... */
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/* turn on ProMedia nvram. */
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/* TO DO: use the PciWriteByte function here. */
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/*
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* the VIA 8231 South has a very different nvram setup than the
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* piix4e ...
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* turn on ProMedia nvram.
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* TO DO: use the PciWriteByte function here.
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*/
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struct pci_dev *dev;
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/*
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* kevinh/Ispiri - I don't think this is the correct address/value
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* intel_conf_writeb(0x80008841, 0xFF);
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*/
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}
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev) {
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pci_write_config_byte(dev, 0x41, 0xc0);
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/*
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* Enable the ethernet device and turn off stepping (because it is integrated
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* inside the southbridge)
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*/
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void ethernet_fixup()
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{
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struct pci_dev *dev, *edev;
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u8 byte;
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printk_info("Ethernet fixup\n");
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edev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
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if (edev != NULL) {
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printk_debug("Configuring VIA LAN\n");
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/* We don't need stepping - though the device supports it */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte &= ~PCI_COMMAND_WAIT;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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} else {
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printk_debug("VIA LAN not found\n");
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}
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}
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void southbridge_fixup()
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{
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unsigned char enables;
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struct pci_dev *dev;
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struct pci_dev *dev0;
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struct pci_dev dev_cpy;
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unsigned int devfn;
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struct pci_dev *dev0;
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struct pci_dev *dev1;
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struct pci_dev *devpwr;
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// to do: use the pcibios_find function here, instead of
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// hard coding the devfn.
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// done - kevinh/Ispiri
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/* Base 8231 controller */
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dev0 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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/* IDE controller */
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dev1 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \
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0);
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/* Power management controller */
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devpwr = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231_4, 0);
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// enable the internal I/O decode
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dev0 = 0;
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dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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if (dev) {
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dev0 = dev;
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memcpy(&dev_cpy, dev, sizeof(dev_cpy));
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pci_read_config_byte(dev, 0x6c, &enables);
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enables |= 0x80;
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pci_write_config_byte(dev, 0x6c, enables);
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} else {
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printk_debug("IDE pci_find_device function 0 failed\n");
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}
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enables = pci_read_config_byte(dev0, 0x6C, &enables);
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enables |= 0x80;
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pci_write_config_byte(dev0, 0x6C, enables);
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// Map 4MB of FLASH into the address space
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pci_write_config_byte(dev0, 0x41, 0x7f);
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// Set bit 6 of 0x40, because Award does it (IO recovery time)
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// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
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// interrupts can be properly marked as level triggered.
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enables = pci_read_config_byte(dev0, 0x40, &enables); enables |= 0x44;
|
||||
pci_write_config_byte(dev0, 0x40, enables);
|
||||
|
||||
// Set 0x42 to 0xf0 to match Award bios
|
||||
enables = pci_read_config_byte(dev0, 0x42, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev0, 0x42, enables);
|
||||
|
||||
// Set bit 3 of 0x4a, to match award (dummy pci request)
|
||||
enables = pci_read_config_byte(dev0, 0x4a, &enables);
|
||||
enables |= 0x08;
|
||||
pci_write_config_byte(dev0, 0x4a, enables);
|
||||
|
||||
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
|
||||
enables = pci_read_config_byte(dev0, 0x4f, &enables);
|
||||
enables |= 0x08;
|
||||
pci_write_config_byte(dev0, 0x4f, enables);
|
||||
|
||||
// Set 0x58 to 0x03 to match Award
|
||||
pci_write_config_byte(dev0, 0x58, 0x03);
|
||||
|
||||
// enable the ethernet/RTC
|
||||
if(dev0) {
|
||||
pci_read_config_byte(dev0, 0x51, &enables);
|
||||
enables |= 0x18;
|
||||
pci_write_config_byte(dev0, 0x51, enables);
|
||||
}
|
||||
|
||||
#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
|
||||
// enable com1 and com2.
|
||||
enables = 0x80 | 0x1 | 0x8 ;
|
||||
if (dev) {
|
||||
pci_write_config_byte(dev, 0x6e, enables);
|
||||
}
|
||||
// note: this is also a redo of some port of assembly, but we
|
||||
// want everything up.
|
||||
enables = pci_read_config_byte(dev0, 0x6e, &enables);
|
||||
// 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable com port a as com1
|
||||
// kevinh/Ispiri - Old code thought 0x01 would make it com1, that was
|
||||
// wrong
|
||||
enables = 0x80 | 0x10 | 0x8 ;
|
||||
pci_write_config_byte(dev0, 0x6e, enables);
|
||||
// note: this is also a redo of some port of assembly, but we want everything up.
|
||||
|
||||
// set com1 to 115 kbaud
|
||||
// not clear how to do this yet.
|
||||
// forget it; done in assembly.
|
||||
|
|
@ -104,81 +211,131 @@ void southbridge_fixup()
|
|||
// enable IDE, since Linux won't do it.
|
||||
// First do some more things to devfn (17,0)
|
||||
// note: this should already be cleared, according to the book.
|
||||
if (dev) {
|
||||
pci_read_config_byte(dev, 0x50, &enables);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev, 0x50, enables);
|
||||
}
|
||||
pci_read_config_byte(dev0, 0x50, &enables);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev0, 0x50, enables);
|
||||
|
||||
// set default interrupt values (IDE)
|
||||
if (dev) {
|
||||
pci_read_config_byte(dev, 0x4c, &enables);
|
||||
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
|
||||
// clear out whatever was there.
|
||||
enables &= ~0xf;
|
||||
enables |= 4;
|
||||
printk_debug("setting reg. 4c to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev, 0x4c, enables);
|
||||
}
|
||||
|
||||
pci_read_config_byte(dev0, 0x4c, &enables);
|
||||
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
|
||||
// clear out whatever was there.
|
||||
enables &= ~0xf;
|
||||
enables |= 4;
|
||||
printk_debug("setting reg. 4c to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev0, 0x4c, enables);
|
||||
|
||||
// set up the serial port interrupts.
|
||||
// com2 to 3, com1 to 4
|
||||
if (dev) {
|
||||
pci_write_config_byte(dev, 0x46, 0x04);
|
||||
pci_write_config_byte(dev, 0x47, 0x03);
|
||||
}
|
||||
pci_write_config_byte(dev0, 0x46, 0x04);
|
||||
pci_write_config_byte(dev0, 0x47, 0x03);
|
||||
|
||||
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
|
||||
if (!dev) {
|
||||
if (dev0) {
|
||||
dev = &dev_cpy;
|
||||
dev_cpy.devfn |= 1;
|
||||
}
|
||||
}
|
||||
if (!dev) {
|
||||
printk_debug("IDE pci_find_device function 1 failed\n");
|
||||
} else {
|
||||
pci_read_config_byte(dev, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config_byte(dev, 0x40, enables);
|
||||
//
|
||||
// Power management setup
|
||||
//
|
||||
// Set ACPI base address to IO 0x4000
|
||||
pci_write_config_dword(devpwr, 0x48, 0x4001);
|
||||
|
||||
pci_read_config_byte(dev, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", \
|
||||
enables);
|
||||
}
|
||||
// Enable ACPI access (and setup like award)
|
||||
pci_write_config_byte(devpwr, 0x41, 0x84);
|
||||
|
||||
// Set hardware monitor base address to IO 0x6000
|
||||
pci_write_config_dword(devpwr, 0x70, 0x6001);
|
||||
|
||||
// Enable hardware monitor (and setup like award)
|
||||
pci_write_config_byte(devpwr, 0x74, 0x01);
|
||||
|
||||
// set IO base address to 0x5000
|
||||
pci_write_config_dword(devpwr, 0x90, 0x5001);
|
||||
|
||||
// Enable SMBus
|
||||
pci_write_config_byte(devpwr, 0xd2, 0x01);
|
||||
|
||||
//
|
||||
// IDE setup
|
||||
//
|
||||
#ifndef ENABLE_IDE_NATIVE_MODE
|
||||
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
|
||||
// interrupts. Using PCI ints confuses linux for some reason.
|
||||
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 0x%x\n", enables);
|
||||
enables &= ~0xc0; // compatability mode
|
||||
pci_write_config_byte(dev1, 0x42, enables);
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config_byte(dev1, 0x40, enables);
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
|
||||
|
||||
// Enable prefetch buffers
|
||||
pci_read_config_byte(dev1, 0x41, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev1, 0x41, enables);
|
||||
|
||||
// Lower thresholds (cause award does it)
|
||||
pci_read_config_byte(dev1, 0x43, &enables);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config_byte(dev1, 0x43, enables);
|
||||
|
||||
// PIO read prefetch counter (cause award does it)
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
|
||||
// Use memory read multiple
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
|
||||
// address decoding.
|
||||
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
|
||||
if (dev) {
|
||||
pci_read_config_byte(dev, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
// by the book, set the low-order nibble to 0xa.
|
||||
enables &= ~0xf;
|
||||
// cf/cg silicon needs an 'f' here.
|
||||
enables |= 0xf;
|
||||
pci_write_config_byte(dev, 0x9, enables);
|
||||
pci_read_config_byte(dev, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
|
||||
// used in native mode - I've changed back to classic
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
// by the book, set the low-order nibble to 0xa.
|
||||
#if ENABLE_IDE_NATIVE_MODE
|
||||
enables &= ~0xf;
|
||||
// cf/cg silicon needs an 'f' here.
|
||||
enables |= 0xf;
|
||||
#else
|
||||
enables &= ~0x5;
|
||||
#endif
|
||||
|
||||
// standard bios sets master bit.
|
||||
pci_read_config_byte(dev, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 5;
|
||||
pci_write_config_byte(dev, 0x4, enables);
|
||||
pci_read_config_byte(dev, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", \
|
||||
enables);
|
||||
// oh well, the PCI BARs don't work right.
|
||||
// This chip will not work unless IDE runs at standard legacy
|
||||
// values.
|
||||
pci_write_config_byte(dev1, 0x9, enables);
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
|
||||
pci_write_config_dword(dev, 0x10, 0x1f1);
|
||||
pci_write_config_dword(dev, 0x14, 0x3f5);
|
||||
pci_write_config_dword(dev, 0x18, 0x171);
|
||||
pci_write_config_dword(dev, 0x1c, 0x375);
|
||||
pci_write_config_dword(dev, 0x20, 0xcc0);
|
||||
}
|
||||
// standard bios sets master bit.
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 7;
|
||||
|
||||
// No need for stepping - kevinh@ispiri.com
|
||||
enables &= ~0x80;
|
||||
|
||||
pci_write_config_byte(dev1, 0x4, enables);
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
|
||||
|
||||
#if (!ENABLE_IDE_NATIVE_MODE)
|
||||
// Use compatability mode - per award bios
|
||||
pci_write_config_dword(dev1, 0x10, 0x0);
|
||||
pci_write_config_dword(dev1, 0x14, 0x0);
|
||||
pci_write_config_dword(dev1, 0x18, 0x0);
|
||||
pci_write_config_dword(dev1, 0x1c, 0x0);
|
||||
|
||||
// Force interrupts to use compat mode - just like Award bios
|
||||
pci_write_config_byte(dev1, 0x3d, 00);
|
||||
pci_write_config_byte(dev1, 0x3c, 0xff);
|
||||
#endif
|
||||
|
||||
ethernet_fixup();
|
||||
|
||||
// Start the rtc
|
||||
rtc_init(0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,10 +2,13 @@
|
|||
* This early setup is a handy place to enable the Ethernet if the user wants
|
||||
* it.
|
||||
*/
|
||||
#if ENABLE_VT8231_LAN
|
||||
enable_eth:
|
||||
movl CONFIG_ADDR(0, SUPERIO_DEVFN, 0x51), %eax
|
||||
movb $0x10, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
#endif
|
||||
movl CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
|
||||
PCI_READ_CONFIG_DWORD
|
||||
|
||||
/* Turn on just the Ethernet */
|
||||
orl $0x1000, %eax
|
||||
mov %eax, %ecx
|
||||
|
||||
movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
|
||||
PCI_WRITE_CONFIG_DWORD
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue