Trying to resync with Eric's changes
First, grow heap size in src/arch/i386/config/ldscript.base for DoC Minor include fixes Fixes to cua -- but it's now broken, won't find IDE Minor fix to util/config/NLBConfig.py: for docipl, use CFLAGS Added files so that CUA works with config tool.
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parent
d3956f5c22
commit
dd99e41d73
13 changed files with 254 additions and 10 deletions
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@ -95,8 +95,8 @@ SECTIONS
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.heap (.): {
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_heap = .;
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/* Reserve 64K for the heap */
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. = . + 0x10000;
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/* Reserve 256K for the heap */
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. = . + 0x40000;
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_eheap = .;
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}
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.stack (.) : {
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@ -35,6 +35,7 @@ static char rcsid[] = "$Id$";
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#include <cpu/p5/io.h>
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#include <intel.h>
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#include <pciconf.h>
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#include <pci.h>
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#include <cpu/p5/cpuid.h>
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#include <cpu/p6/ioapic.h>
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#include <subr.h>
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@ -48,6 +49,11 @@ void intel_main()
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void keyboard_on(void);
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void framebuffer_on(void);
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void intel_copy_irq_routing_table(void);
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unsigned long sizeram(void);
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void intel_cache_on(unsigned long base, unsigned long totalram);
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void intel_zero_irq_settings(void);
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void intel_check_irq_routing_table(void);
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void intel_interrupts_on();
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#ifdef FINAL_MAINBOARD_FIXUP
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void final_mainboard_fixup(void);
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@ -117,12 +117,12 @@ void error(char errmsg[])
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*/
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void post_code(uint8_t value)
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{
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unsigned long hi, lo;
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outb(value, 0x80);
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#ifdef SERIAL_POST
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unsigned long hi, lo;
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rdtsc(lo, hi);
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printk(KERN_INFO "POST: 0x%02x, TSC Lo: %d, Hi: %d\n",
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value, lo, hi);
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#endif
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outb(value, 0x80);
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}
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12
src/mainboard/asus/cua/Config
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12
src/mainboard/asus/cua/Config
Normal file
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@ -0,0 +1,12 @@
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northbridge acer/m1631
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southbridge acer/m1535
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superio acer/m1535
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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option FINAL_MAINBOARD_FIXUP
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option HAVE_PIRQ_TABLE
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object mainboard.o
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object irq_tables.o
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keyboard pc80
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cpu p5
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cpu p6
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31
src/mainboard/asus/cua/irq_tables.c
Normal file
31
src/mainboard/asus/cua/irq_tables.c
Normal file
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@ -0,0 +1,31 @@
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#include <i386_subr.h>
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/* NOTE -- THIS IS A PLACEHOLDER -- WE NEED TO FIX THIS */
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#define CHECKSUM 0xe6
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0x00, /* Bus 0 */
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0x08, /* Device 1, Function 0 */
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0x0A20, /* reserve IRQ 11, 9, 5, for PCI */
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0x1039, /* Silicon Integrated System */
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0x0008, /* SiS 85C503/5513 ISA Bridge */
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0x00, /* u8 miniport_data - "crap" */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
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{
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/* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}},
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0x01, 0x00},
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{0x00, 0x60, {{0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}},
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0x02, 0x00},
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{0x00, 0x01, {{0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x0a, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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}
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};
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@ -5,12 +5,10 @@
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void mainboard_fixup()
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{
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struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
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unsigned smbus_io, pm_io;
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unsigned int i, j;
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printk("intel_mainboard_fixup()\n");
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printk("intel_mainboard_fixup()\n");
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#if 0
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struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
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// put in the right values for acer stuff
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pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
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nic_pcidev = pci_find_device(0x8086, 0x1229, 0);
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1
src/northbridge/acer/m1631/Config
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1
src/northbridge/acer/m1631/Config
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@ -0,0 +1 @@
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object northbridge.o
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@ -1,5 +1,5 @@
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#include <pci.h>
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#include <printk.h>
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// FIX ME!
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unsigned long sizeram()
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@ -15,8 +15,13 @@ void intel_framebuffer_on()
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}
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#endif
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void
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final_northbridge_fixup()
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{
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printk("SET THAT BIT!\n");
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/* set bit 4 of north bridge register d4 to 1 */
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}
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2
src/southbridge/acer/m1535/Config
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2
src/southbridge/acer/m1535/Config
Normal file
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@ -0,0 +1,2 @@
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object southbridge.o
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108
src/superio/acer/m1535/setup_serial.inc
Normal file
108
src/superio/acer/m1535/setup_serial.inc
Normal file
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@ -0,0 +1,108 @@
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/*
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* setup_serial.inc: setup serial port for m1535
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*
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*
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* Copyright 2001 Acer Labs Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference:
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* 1. M1535D document
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* $Id$
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*/
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/*
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* Super I/O Logical Device 4 (UART1)
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Reg 0x30 [0] = 1 -- UART1 Enable
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Reg 0x60 [7:0] = 0x03 -- The high address UART1's I/O base address
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Reg 0x61 [7:0] = 0xF8 -- The low address UART1's I/O base address
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Reg 0x70 [7:0] = 0x04 -- IRQ[4]
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Reg 0xF0 [7:0] = 0x00
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Reg 0xf1 [7:0] = 0x00
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Reg 0xf2 [7:0] = 0x00
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assume I/O port address is 0x3F0
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*/
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// 1 ;enter configuration mode
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movw $0x3f0,%dx
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movb $0x51,%al
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outb %al,%dx
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movw $0x23,%ax
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outb %al,%dx
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// 2 ;program logical device 4
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movw $0x3f0,%dx
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movb $0x07,%al
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outb %al,%dx //point to device select register
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movw $0x3f1,%dx
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movb $0x04,%al
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outb %al,%dx //point to device 4
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movw $0x3f0,%dx
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movb $0x30,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x01,%al
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outb %al,%dx //enable UART1 controller
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movw $0x3f0,%dx
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movb $0x60,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x03,%al
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outb %al,%dx
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movw $0x3f0,%dx
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movb $0x61,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0xf8,%al
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outb %al,%dx //select UART1's I/O base address to $0x3F$0x8
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movw $0x3f0,%dx
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movb $0x70,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x04,%al
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outb %al,%dx //select IRQ 4 used by UART1
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movw $0x3f0,%dx
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movb $0xf0,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x00,%al
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outb %al,%dx
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movw $0x3f0,%dx
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movb $0xf1,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x00,%al
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outb %al,%dx
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movw $0x3f0,%dx
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movb $0xf2,%al
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outb %al,%dx
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movw $0x3f1,%dx
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movb $0x00,%al
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outb %al,%dx
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// 3. exit configuration mode
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movw $0x3f0,%dx
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movb $0xbb,%al
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outb %al,%dx
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58
src/superio/acer/m1535/superio.c
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58
src/superio/acer/m1535/superio.c
Normal file
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@ -0,0 +1,58 @@
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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// just define these here. We may never need them anywhere else
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#define PNP_COM1_DEVICE 0x1
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#define PNP_COM2_DEVICE 0x2
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#include <subr.h>
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#include <cpu/p5/io.h>
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void
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enter_pnp(void)
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{
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}
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void
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exit_pnp(void)
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{
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}
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#ifdef MUST_ENABLE_FLOPPY
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void
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enable_floppy(void)
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{
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}
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#endif /* MUST_ENABLE_FLOPPY */
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void
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enable_com(int com)
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{
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}
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#ifdef MUST_ENABLE_LPT
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void
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enable_lpt(void)
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{
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}
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#endif /* MUST_ENABLE_LPT */
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void
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final_superio_fixup(void)
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{
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enter_pnp();
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#ifdef MUST_ENABLE_FLOPPY
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enable_floppy();
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#endif /* MUST_ENABLE_LPT */
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enable_com(PNP_COM1_DEVICE);
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enable_com(PNP_COM2_DEVICE);
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#ifdef MUST_ENABLE_LPT
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enable_lpt();
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#endif /* MUST_ENABLE_LPT */
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exit_pnp();
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}
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@ -254,7 +254,7 @@ def docipl(dir, ipl_name):
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iplpath = os.path.join(treetop, 'src', ipl_name)
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userrules.append("ipl.o: " + iplpath)
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# Now we need a mainboard-specific include path
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userrules.append("\tcc $(CPUFLAGS) -I%s -c $<" % mainboard_dir)
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userrules.append("\tcc $(CFLAGS) -I%s -c $<" % mainboard_dir)
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# now set new values for the ldscript.ld. Should be a script?
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rambase = 0x4000
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linuxbiosbase = 0x80000
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23
util/config/asus_cua_doc.config
Normal file
23
util/config/asus_cua_doc.config
Normal file
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# Sample config file for ASUS CUA with DoC Millennium (as root)
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arch i386
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# This will make a target directory of ./winfast
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target asus_cua
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# Asus CUA
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mainboard asus/cua
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option CONFIGURE_L2_CACHE
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# Use the internal VGA frame buffer device
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# option HAVE_FRAMEBUFFER
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# Path to your kernel (vmlinux)
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linux /usr/src/linux
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# Kernel command line parameters
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commandline root=/dev/hda1 console=ttyS0,115200 console=tty0 single
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