more geode support
This commit is contained in:
Ronald G. Minnich
parent
41b15b89b3
commit
f6ff7bc4e2
22 changed files with 1586 additions and 22 deletions
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@ -384,10 +384,14 @@ static int build_elf_segment_list(
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new->s_memsz = phdr[i].p_memsz;
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new->s_offset = phdr[i].p_offset;
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new->s_filesz = phdr[i].p_filesz;
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printk_debug("New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
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new->s_addr, new->s_memsz, new->s_offset, new->s_filesz);
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/* Clean up the values */
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if (new->s_filesz > new->s_memsz) {
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new->s_filesz = new->s_memsz;
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}
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printk_debug("(cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
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new->s_addr, new->s_memsz, new->s_offset, new->s_filesz);
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for(ptr = head->next; ptr != head; ptr = ptr->next) {
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if (new->s_offset < ptr->s_offset)
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break;
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@ -567,8 +571,10 @@ int elfload(struct stream *stream, struct lb_memory *mem,
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goto out;
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/* Verify the loaded image */
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/*
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if (!verify_loaded_image(cb_chain, ehdr, phdr, &head))
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goto out;
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*/
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/* Shutdown the stream device */
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stream->fini();
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82
src/mainboard/cocom/voyager2/Config
Normal file
82
src/mainboard/cocom/voyager2/Config
Normal file
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@ -0,0 +1,82 @@
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# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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# This is a config file for the Cocom Voyager 2 board
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# <URL:http://www.cocom.co.uk>
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# The Voyager 2 is a National Semiconductor GX1 + CS5530 + PC93917
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# design. It is a fairly complete PC with VGA, one serial port, one
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# IrDA header, one parallel port, two USB ports, a PS/2 Keyboard
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# connector (can also be used for a PS/2 Mouse using a splitter
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# cable), floppy, IDE and finally one ethernet port using a RTL8139
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# ethernet chip. Other than that the board has a DiskOnChip socket
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# and a PC104 connector for expansion.
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arch i386
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cpu p5
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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########################################################################
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mainboardinit superio/NSC/pc97317/sio_setup.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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########################################################################
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northbridge nsc/gx1
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southbridge nsc/cs5530
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superio NSC/pc97317
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########################################################################
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# Lots of constans, you probably don't need to change anything here.
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# GX_BASE is the address of a configuration memory region for the GX1
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# processor. You probably don't want to change this.
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option GX_BASE=0x40000000
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########################################################################
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# Super I/O configuration
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# The SIO is pin strapped to show up at address 0x2e
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option SIO_BASE=0x2e
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# Serial Port 1
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option SIO_SP1_BASE=0x3f8
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option SIO_SP1_IRQ=4
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# Serial Port 2 is connected to an IrDA header
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#option SIO_SP2_BASE=0x2f8
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#option SIO_SP2_IRQ=3
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# Parallel port
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option SIO_PP_BASE=0x278
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option SIO_PP_IRQ=7
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# GPIO Pins
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option SIO_GPIO_BASE=0xe0
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########################################################################
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# Southbridge configuration
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option CS5530_INTA=9
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option CS5530_INTB=10
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option CS5530_INTC=11
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option CS5530_INTD=15
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option CS5530_PRIMARY_IDE=1
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#option CS5530_SECONDARY_IDE=1
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########################################################################
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option NO_KEYBOARD
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option FINAL_MAINBOARD_FIXUP=1
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object mainboard.o
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# Local variables:
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# compile-command: "make -C /export/bios/voyager2"
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# End:
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33
src/mainboard/cocom/voyager2/config.example
Normal file
33
src/mainboard/cocom/voyager2/config.example
Normal file
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@ -0,0 +1,33 @@
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# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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# This is an example configuration file for the Cocom Voyager 2
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# See src/mainboard/cocom/voyager2/Config for more information
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target voyager2
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mainboard cocom/voyager2
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE=1
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option TTYS0_BAUD=38400
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option DEFAULT_CONSOLE_LOGLEVEL=9
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option DEBUG
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#option INBUF_COPY
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option RAMTEST
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#option BOOT_IDE=1
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#option BOOT_TFTP=1
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#option USE_ELF_BOOT=1
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option USE_GENERIC_ROM=1
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option ZKERNEL_START=0xc0000200
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option ZKERNEL_MASK=0xffff
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option ROM_SIZE=262144
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# Path to your kernel (vmlinux)
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linux /export/nano/linux
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# Kernel command line parameters
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commandline root=/dev/hda2 console=ttyS0,38400 reboot=h
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#commandline root=/dev/nfs ip=dhcp console=ttyS0,38400
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48
src/mainboard/cocom/voyager2/mainboard.c
Normal file
48
src/mainboard/cocom/voyager2/mainboard.c
Normal file
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@ -0,0 +1,48 @@
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/*
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freebios/src/mainboard/cocom/voyager2/mainboard.c
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Mainboard fixup for the Cocom Voyager 2
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*/
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#include <printk.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <cpu/p5/io.h>
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#include <types.h>
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void
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mainboard_fixup()
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{
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}
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void
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final_mainboard_fixup()
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{
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#if 0
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struct pci_dev *dev;
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int i;
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#endif
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void final_southbridge_fixup(void);
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final_southbridge_fixup();
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printk_info("Final mainboard fixup\n");
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#if 0
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dev = pci_find_slot(0, PCI_DEVFN(0x0f, 0));
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if (dev) {
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printk_debug("nano: Setting eth0 IRQ to %d\n", SCx200_INTA);
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, SCx200_INTA);
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}
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#endif
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}
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/*
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Local variables:
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compile-command: "make -C /export/bios/voyager2"
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c-basic-offset: 8
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End:
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*/
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@ -13,6 +13,7 @@
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# for debugging and not really for production use.
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arch i386
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cpu p5
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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@ -20,6 +21,18 @@ ldscript cpu/i386/entry32.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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########################################################################
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mainboardinit southbridge/nsc/scx200/scx200_setup.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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########################################################################
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# Just about everything is integrated in the SCx200
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northbridge nsc/gx1
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southbridge nsc/scx200
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########################################################################
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# Where the Disk On Chip Chip Select pin is mapped in memory.
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# See the SCx200 databook for more information.
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@ -97,30 +110,11 @@ option SCx200_PRIMARY_IDE
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#option SCx200_SECONDARY_IDE
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########################################################################
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# Finally, the code
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# This must be done before the serial port is initialized, so
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# it has to be here.
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mainboardinit northsouthbridge/NSC/scx200/chipset_setup.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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northsouthbridge NSC/scx200
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option NO_KEYBOARD
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option FINAL_MAINBOARD_FIXUP=1
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object mainboard.o
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# The PIRQ table doesn't seem to work properly, so the PCI interrupts
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# are set up in final_mainboard_fixup instead.
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# FIXME -- build a working irq table
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#option HAVE_PIRQ_TABLE=1
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#object irq_tables.o
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cpu p5
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# Local variables:
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# compile-command: "make -C /export/nano/bios/nano"
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# compile-command: "make -C /export/bios/nano"
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# End:
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@ -29,6 +29,11 @@ option RAMTEST
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# DOC socket that causes it to write garbage to address 0x80 of the
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# flash chip.
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# For some strange reason the kernel fails to boot when I use a high ROMBASE
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#option _ROMBASE=0xffff0000
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#option USE_ELF_BOOT=1
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option USE_GENERIC_ROM=1
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option ZKERNEL_START=0xc0000200
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option ZKERNEL_MASK=0xffff
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@ -45,7 +50,7 @@ option ROM_SIZE=262144
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linux /export/nano/linux
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# Kernel command line parameters
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commandline root=/dev/hda2 console=ttyS0,38400
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commandline root=/dev/hda2 console=ttyS0,38400 reboot=h
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#commandline root=/dev/nfs ip=dhcp console=ttyS0,38400
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@ -75,7 +75,7 @@ final_mainboard_fixup()
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/*
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Local variables:
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compile-command: "make -C /export/nano/bios/nano"
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compile-command: "make -C /export/bios/nano"
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c-basic-offset: 8
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End:
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*/
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12
src/northbridge/nsc/gx1/Config
Normal file
12
src/northbridge/nsc/gx1/Config
Normal file
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@ -0,0 +1,12 @@
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# freebios/src/northbridge/nsc/gx1/Config
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# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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# Configuration for the National Semiconductor GX1 processors
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mainboardinit northbridge/nsc/gx1/cpu_setup.inc
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mainboardinit northbridge/nsc/gx1/gx_setup.inc
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mainboardinit northbridge/nsc/gx1/northbridge_setup.inc
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raminit northbridge/nsc/gx1/raminit.inc
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object northbridge.o
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66
src/northbridge/nsc/gx1/cpu_setup.inc
Normal file
66
src/northbridge/nsc/gx1/cpu_setup.inc
Normal file
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@ -0,0 +1,66 @@
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/*
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freebios/src/northbridge/nsc/gx1/cpu_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Initialize the GX1 CPU configuration registers
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*/
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cpu_setup_start:
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leal cpu_setup_table, %esi
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movl $cpu_setup_len, %ecx
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cpu_setup_loop:
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movw (%esi), %ax
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addl $2, %esi
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outb %al, $0x22
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movb %ah, %al
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outb %al, $0x23
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loop cpu_setup_loop
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movb $0xff, %al /* DIR1 -- Identification Register 1 */
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outb %al, $0x22
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inb $0x23, %al
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cmpb $0x63, %al /* Revision for GXLV rev 3 */
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jbe cpu_no_ccr4
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movb $0xe8, %al /* CCR4 */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Enable FPU Fast Mode */
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outb %al, $0x23
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movb $0xf0, %al /* PCR1 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x02, %al /* Incrementor on, whatever that is */
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outb %al, $0x23
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movb $0x20, %al /* PCR0 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Must be 1 according to data book */
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orb $0x04, %al /* Incrementor Margin 10 */
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outb %al, $0x23
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cpu_no_ccr4:
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jmp cpu_setup_end
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cpu_setup_table:
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.byte 0xc1, 0x00 /* NO SMIs */
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.byte 0xc3, 0x14 /* Enable CPU config register */
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.byte 0x20, 0x00
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.byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */
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.byte 0xc2, 0x00
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.byte 0xe8, 0x98
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.byte 0xc3, 0xf8 /* Enable CPU config register */
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cpu_setup_len = (.-cpu_setup_table)/2
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cpu_setup_end:
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nop
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/*
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Local variables:
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compile-command: "make -C /export/bios/voyager2"
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End:
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*/
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52
src/northbridge/nsc/gx1/gx1def.h
Normal file
52
src/northbridge/nsc/gx1/gx1def.h
Normal file
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@ -0,0 +1,52 @@
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/*
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freebios/src/northbridge/nsc/gx1/gx1def.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Defines for the GX1 processor
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*/
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/**********************************************************************/
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/* Display Controller Registers, offset from GX_BASE */
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#define DC_UNLOCK 0x8300
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#define DC_UNLOCK_MAGIC 0x4758
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#define DC_GENERAL_CFG 0x8304
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/**********************************************************************/
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/* Bus Controller Registers, offset from GX_BASE */
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#define BC_DRAM_TOP 0x8000
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#define BC_XMAP_1 0x8004
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#define BC_XMAP_2 0x8008
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#define BC_XMAP_3 0x800c
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/**********************************************************************/
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/* Memory Controller Registers, offset from GX_BASE */
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#define MC_MEM_CNTRL1 0x8400
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#define SDCLKSTRT (1<<17)
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#define RFSHRATE (0x1ff<<8)
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#define RFSHSTAG (0x3<<6)
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#define X2CLKADDR (1<<5)
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#define RFSHTST (1<<4)
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#define XBUSARB (1<<3)
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#define SMM_MAP (1<<2)
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#define PROGRAM_SDRAM (1<<0)
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#define MC_MEM_CNTRL2 0x8404
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#define SDCLK_MASK 0x000003c0
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#define SDCLKOUT_MASK 0x00000400
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#define MC_BANK_CFG 0x8408
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#define DIMM_PG_SZ 0x00000070
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#define DIMM_SZ 0x00000700
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#define DIMM_COMP_BNK 0x00001000
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#define DIMM_MOD_BNK 0x00004000
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#define MC_SYNC_TIM1 0x840c
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#define MC_GBASE_ADD 0x8414
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49
src/northbridge/nsc/gx1/gx_setup.inc
Normal file
49
src/northbridge/nsc/gx1/gx_setup.inc
Normal file
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@ -0,0 +1,49 @@
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/*
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freebios/src/northbridge/nsc/gx1/gx_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Setup the GX_BASE registers on a National Semiconductor Geode CPU
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*/
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#include "gx1def.h"
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gx_setup_start:
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leal gx_setup_table, %esi
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movl $gx_setup_len, %ecx
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movl $GX_BASE, %edi
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gx_setup_loop:
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movw (%esi), %di /* Only read the low word of address */
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addl $4, %esi
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movl (%esi), %eax /* Data */
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addl $4, %esi
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movl %eax, (%edi)
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loop gx_setup_loop
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jmp gx_setup_end
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gx_setup_table:
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/* Allow writes to config registers */
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.long DC_UNLOCK, DC_UNLOCK_MAGIC
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.long DC_GENERAL_CFG, 0
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.long DC_UNLOCK, 0
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.long BC_DRAM_TOP, 0x3fffffff
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.long BC_XMAP_1, 0x60
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.long BC_XMAP_2, 0
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.long BC_XMAP_3, 0
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.long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */
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.long MC_MEM_CNTRL1, XBUSARB
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.long MC_GBASE_ADD, 0x7ff /* Almost 1GB */
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gx_setup_len = (.-gx_setup_table)/8
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gx_setup_end:
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nop
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
End:
|
||||
*/
|
||||
82
src/northbridge/nsc/gx1/northbridge.c
Normal file
82
src/northbridge/nsc/gx1/northbridge.c
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
freebios/src/northbridge/nsc/gx1/northbridge.c
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Do chipset setup for a National Semiconductor GX1 CPU.
|
||||
*/
|
||||
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
|
||||
#include "gx1def.h"
|
||||
|
||||
#define __io_virt(addr) (addr)
|
||||
|
||||
#define readb(addr) (*(volatile unsigned char *) __io_virt(addr))
|
||||
#define readw(addr) (*(volatile unsigned short *) __io_virt(addr))
|
||||
#define readl(addr) (*(volatile unsigned int *) __io_virt(addr))
|
||||
|
||||
#define writeb(b,addr) (*(volatile unsigned char *) __io_virt(addr) = (b))
|
||||
#define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b))
|
||||
#define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b))
|
||||
|
||||
static unsigned calc_dimm(int index, unsigned cfg)
|
||||
{
|
||||
if (((cfg >> 4) & 7) == 7) {
|
||||
printk_info("DIMM%d: empty\n", index);
|
||||
return 0;
|
||||
} else {
|
||||
unsigned page_size = 1 << ((cfg >> 4) & 7);
|
||||
unsigned dimm_size = 4 << ((cfg >> 8) & 7);
|
||||
unsigned comp_bank = 2 << ((cfg >> 12) & 1);
|
||||
unsigned module_bank = 1 << ((cfg >> 14) & 1);
|
||||
|
||||
printk_info("DIMM%d: %uMB (%ukB page size, %d component banks, %u module banks)\n",
|
||||
index, dimm_size, page_size, comp_bank, module_bank);
|
||||
return dimm_size * 1024;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long adjust_video_memory(unsigned long mem_size)
|
||||
{
|
||||
unsigned video_size = 4096;
|
||||
|
||||
printk_info("Reserving %dkB for video memory\n", video_size);
|
||||
|
||||
/* Adjust for video memory size */
|
||||
mem_size -= video_size;
|
||||
|
||||
/* Set up the registers */
|
||||
writel(mem_size * 1024 - 1, GX_BASE + BC_DRAM_TOP);
|
||||
writel(mem_size / 512, GX_BASE + MC_GBASE_ADD);
|
||||
|
||||
printk_debug("BC_DRAM_TOP = 0x%08x\n", readl(GX_BASE + BC_DRAM_TOP));
|
||||
printk_debug("MC_GBASE_ADD = 0x%08x\n", readl(GX_BASE + MC_GBASE_ADD));
|
||||
|
||||
return mem_size;
|
||||
}
|
||||
|
||||
unsigned long sizeram()
|
||||
{
|
||||
u32 mem_bank_cfg;
|
||||
unsigned mem_size;
|
||||
|
||||
mem_bank_cfg = *(volatile unsigned long *)(GX_BASE+0x8408);
|
||||
|
||||
mem_size = 0;
|
||||
mem_size += calc_dimm(0, mem_bank_cfg);
|
||||
mem_size += calc_dimm(1, mem_bank_cfg >> 16);
|
||||
|
||||
mem_size = adjust_video_memory(mem_size);
|
||||
|
||||
return mem_size;
|
||||
}
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
c-basic-offset: 8
|
||||
End:
|
||||
*/
|
||||
48
src/northbridge/nsc/gx1/northbridge_setup.inc
Normal file
48
src/northbridge/nsc/gx1/northbridge_setup.inc
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
freebios/src/northbridge/nsc/gx1/bridge_setup.inc
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Setup the northbridge of a National Semiconductor GX1 CPU.
|
||||
*/
|
||||
|
||||
northbridge_setup:
|
||||
leal northbridge_setup_table, %esi
|
||||
movl $northbridge_setup_len, %ecx
|
||||
movl $0x80000000, %ebx /* Host Bridge Config Space */
|
||||
|
||||
northbridge_setup_loop:
|
||||
movb (%esi), %bl
|
||||
incl %esi
|
||||
movb (%esi), %al
|
||||
incl %esi
|
||||
|
||||
movw $0xcf8, %dx /* PCI Write Config Byte */
|
||||
xchgl %ebx, %eax
|
||||
outl %eax, %dx
|
||||
movw %ax, %dx
|
||||
andw $3, %dx
|
||||
orw $0xcfc, %dx
|
||||
xchgl %ebx, %eax
|
||||
outb %al, %dx
|
||||
|
||||
loop northbridge_setup_loop
|
||||
|
||||
jmp northbridge_setup_end
|
||||
|
||||
northbridge_setup_table:
|
||||
/* I belive this optimizes for X-bus performance */
|
||||
.byte 0x40, 0x1e
|
||||
.byte 0x41, 0x52
|
||||
.byte 0x43, 0xc1 /* PCI arbitration 1 */
|
||||
.byte 0x44, 0x00 /* PCI arbitration 2 */
|
||||
northbridge_setup_len = (.-northbridge_setup_table)/2
|
||||
|
||||
northbridge_setup_end:
|
||||
nop
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
End:
|
||||
*/
|
||||
454
src/northbridge/nsc/gx1/raminit.inc
Normal file
454
src/northbridge/nsc/gx1/raminit.inc
Normal file
|
|
@ -0,0 +1,454 @@
|
|||
/*
|
||||
freebios/src/northbridge/nsc/gx1/raminit.inc
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Do memory sizing for a National Semiconductor GX1 CPU.
|
||||
*/
|
||||
|
||||
#include "gx1def.h"
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
#define TEST_DATA1 0x05A5A5A5A
|
||||
#define TEST_DATA2 0x0DEADBEEF
|
||||
|
||||
#define NUM_REFRESH 8
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ram_setup:
|
||||
CONSOLE_DEBUG_TX_STRING($str_setup_default_memory)
|
||||
|
||||
/* Set up Memory controller, note that all the code below
|
||||
assumes that the high word of %edi contains GX_BASE */
|
||||
movl $GX_BASE, %edi
|
||||
|
||||
movw $MC_MEM_CNTRL2, %di
|
||||
movl $0x000007d8, (%edi) /* Disable all SDCLKs, Shift = 3 */
|
||||
|
||||
movw $MC_MEM_CNTRL1, %di
|
||||
movl $0x92140000, (%edi) /* MD_DS=2, MA_DS=2, CNTL_DS=2
|
||||
SDCLKRATE=/4 */
|
||||
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl $0x00700070, (%edi) /* No DIMMS installed */
|
||||
|
||||
movw $MC_SYNC_TIM1, %di
|
||||
movl $0x3A733225, (%edi) /* LTMODE 3, RC 10, RAS 7, RP 3,
|
||||
RCD 3, RRD 2, DPL 2 */
|
||||
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl $0x57405740, (%edi) /* Largest possible DIMMS installed
|
||||
0x4000 -- 2 module banks
|
||||
0x1000 -- 4 component banks
|
||||
0x0700 -- DIMM size 512MB
|
||||
0x0040 -- Page Size 16kB */
|
||||
|
||||
CALLSP(enable_dimm) /* Program the DIMM's */
|
||||
|
||||
CONSOLE_DEBUG_TX_STRING($str_sizing_memory)
|
||||
|
||||
/* EBP will contain the DIMM configuration after we're done.
|
||||
To begin with, it is set up for no DIMMs at all */
|
||||
movl $0x00700070, %ebp
|
||||
|
||||
/* Parameters for DIMM0 */
|
||||
movl $0x00705740, %edx /* DIMM0 is maxed, no DIMM0 */
|
||||
movb $0, %cl /* Shift value DIMM0=0, DIMM1=16 */
|
||||
|
||||
dimm_loop:
|
||||
movl %edx, %esi
|
||||
CONSOLE_INFO_TX_STRING($str_probing)
|
||||
movb %cl, %al
|
||||
rorb $4, %al
|
||||
addb $'0', %al
|
||||
CONSOLE_INFO_TX_CHAR(%al)
|
||||
CONSOLE_INFO_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
|
||||
/* First configure the memory with the new settings */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl %edx, (%edi)
|
||||
CALLSP(do_refresh)
|
||||
|
||||
/* Write something to location 0 and read it back */
|
||||
movl $TEST_DATA1, 0 /* Write data to location 0 */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl 0, %eax /* Read data from location 0 */
|
||||
movl $0, 0 /* Clear location 0 */
|
||||
|
||||
/* If we got the same value back, there is memory in the bank */
|
||||
cmpl $TEST_DATA1, %eax
|
||||
jne next_dimm
|
||||
|
||||
movl $TEST_DATA2, 0 /* Write data to location 0 */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl 0, %eax /* Read data from location 0 */
|
||||
movl $0, 0 /* Clear location 0 */
|
||||
|
||||
cmpl $TEST_DATA2, %eax
|
||||
jne next_dimm
|
||||
|
||||
#ifdef DEBUG
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_found)
|
||||
movb %cl, %al
|
||||
rorb $4, %al
|
||||
addb $'0', %al
|
||||
CONSOLE_DEBUG_TX_CHAR(%al)
|
||||
CONSOLE_DEBUG_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
#endif
|
||||
|
||||
/* Do page size detection, read the NatSemi reference drivers for an
|
||||
explanation of how it works */
|
||||
|
||||
movl $0x0040, %ebx /* MC_BANK_CFG for 16kB page size */
|
||||
movl $0x2000, %esi /* Offset: 16kB/2 */
|
||||
|
||||
page_size_loop:
|
||||
movl $TEST_DATA1, 0 /* Write data to location 0 */
|
||||
movl $TEST_DATA2, (%esi) /* Write to page size/2 */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl 0, %eax /* Read data from location 0 */
|
||||
movl $0, 0 /* Clear location 0 */
|
||||
|
||||
cmpl $TEST_DATA1, %eax /* If no aliasing, we have found */
|
||||
je page_size_found /* out the page size */
|
||||
|
||||
/* We had aliasing, so go to the next smaller setting */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl (%edi), %edx /* Get current MC_BANK_CFG settings */
|
||||
movl $~DIMM_PG_SZ, %eax /* Mask for the page size */
|
||||
roll %cl, %eax /* Shift for the right DIMM */
|
||||
andl %eax, %edx /* Do the masking */
|
||||
subl $0x10,%ebx /* Select the next smaller page size */
|
||||
jc mem_sizing_failed /* Nothing matched, we've failed */
|
||||
shll %cl, %ebx /* Shift for the right DIMM */
|
||||
orl %ebx, %edx /* And merge it into the settings */
|
||||
shrl %cl, %ebx /* And shift it back again */
|
||||
shrl $1, %esi /* Divide test address by 2 */
|
||||
|
||||
movl %edx, (%edi) /* Use the new MC_BANK_CFG settings */
|
||||
CALLSP(do_refresh)
|
||||
jmp page_size_loop
|
||||
|
||||
page_size_found:
|
||||
/* Save the page size we found in EBP */
|
||||
movl $~DIMM_PG_SZ, %eax
|
||||
roll %cl, %eax
|
||||
andl %eax, %ebp
|
||||
movl %ebx, %eax
|
||||
shll %cl, %eax
|
||||
or %eax, %ebp
|
||||
|
||||
#ifdef DEBUG
|
||||
shll $1, %esi
|
||||
movw %si, %di
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_page_size)
|
||||
xorl %eax, %eax
|
||||
movw %di, %ax
|
||||
CONSOLE_DEBUG_TX_HEX32(%eax)
|
||||
CONSOLE_DEBUG_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
#endif
|
||||
|
||||
/* Do component banks detection */
|
||||
movl $0x0800, %esi /* Smallest page = 1KB * 2 banks */
|
||||
|
||||
shll $16, %ecx /* Save DIMM shift */
|
||||
movl %ebp, %eax /* Get the DIMM values */
|
||||
shrl %cl, %eax /* shifted back */
|
||||
|
||||
movw %ax, %cx /* Use the MC_BANK_CFG */
|
||||
shrw $4, %cx /* page size setting as */
|
||||
andb $7, %cl /* a shift to calculate */
|
||||
shll %cl, %esi /* the page size */
|
||||
|
||||
shrl $16, %ecx /* Restore DIMM shift */
|
||||
|
||||
movl $TEST_DATA1, 0 /* Write data to location 0 */
|
||||
movl $TEST_DATA2, (%esi) /* Write to next page */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl 0, %eax /* Read data from location 0 */
|
||||
|
||||
cmpl $TEST_DATA1, %eax /* If no aliasing, */
|
||||
je component_banks_4 /* there are 4 banks */
|
||||
|
||||
/* Reconfigure the memory controller for 2 banks */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl (%edi), %edx
|
||||
movl $~DIMM_COMP_BNK, %eax /* Mask for component banks */
|
||||
roll %cl, %eax /* shifted */
|
||||
andl %eax, %ebp /* clear the bit of EBP */
|
||||
andl %eax, %edx /* clear the bit of EDX */
|
||||
movl %edx, (%edi) /* Use new settings */
|
||||
CALLSP(do_refresh)
|
||||
#ifdef DEBUG
|
||||
movw $'2',%di
|
||||
#endif
|
||||
jmp component_banks_done
|
||||
|
||||
component_banks_4:
|
||||
movl $DIMM_COMP_BNK, %eax /* Set the bit of EBP */
|
||||
roll %cl, %eax /* shifted */
|
||||
orl %eax, %ebp
|
||||
#ifdef DEBUG
|
||||
movw $'4',%di
|
||||
#endif
|
||||
component_banks_done:
|
||||
#ifdef DEBUG
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_component_banks)
|
||||
movw %di, %ax
|
||||
CONSOLE_DEBUG_TX_CHAR(%al)
|
||||
CONSOLE_DEBUG_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
#endif
|
||||
|
||||
/* Do module banks detection */
|
||||
movl $0x0800, %esi /* Smallest page = 1KB * 2 banks */
|
||||
|
||||
shll $16, %ecx /* Save DIMM shift */
|
||||
movl %ebp, %eax /* Get the DIMM values */
|
||||
shrl %cl, %eax /* shifted back */
|
||||
|
||||
movw %ax, %cx /* Use the MC_BANK_CFG */
|
||||
shrw $4, %cx /* page size setting as */
|
||||
andb $7, %cl /* a shift to calculate */
|
||||
shll %cl, %esi /* the page size */
|
||||
|
||||
movw %ax, %cx /* Use the MC_BANK_CFG */
|
||||
shrw $12, %cx /* component bank setting */
|
||||
andb $1, %cl /* a shift to calculate */
|
||||
shll %cl, %esi /* the total bank size */
|
||||
|
||||
shrl $16, %ecx /* Restore DIMM shift */
|
||||
|
||||
movl $TEST_DATA1, 0 /* Write data to location 0 */
|
||||
movl $TEST_DATA2, (%esi) /* Write to module bank 2 */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl (%esi), %eax /* Read from module bank 2 */
|
||||
|
||||
cmpl $TEST_DATA2, %eax /* If good data, */
|
||||
je module_banks_2 /* there are 2 module banks */
|
||||
|
||||
/* Reconfigure the memory controller for 1 module bank */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl (%edi), %edx
|
||||
movl $~DIMM_MOD_BNK, %eax /* Mask for module banks */
|
||||
roll %cl, %eax /* shifted */
|
||||
andl %eax, %ebp /* clear the bit of EBP */
|
||||
andl %eax, %edx /* clear the bit of EDX */
|
||||
movl %edx, (%edi) /* Use new settings */
|
||||
CALLSP(do_refresh)
|
||||
#ifdef DEBUG
|
||||
movw $'1',%di
|
||||
#endif
|
||||
jmp module_banks_done
|
||||
|
||||
module_banks_2:
|
||||
movl $DIMM_MOD_BNK, %eax /* Set the bit of EBP */
|
||||
roll %cl, %eax /* shifted */
|
||||
orl %eax, %ebp
|
||||
#ifdef DEBUG
|
||||
movw $'2',%di
|
||||
#endif
|
||||
module_banks_done:
|
||||
#ifdef DEBUG
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_module_banks)
|
||||
movw %di, %ax
|
||||
CONSOLE_DEBUG_TX_CHAR(%al)
|
||||
CONSOLE_DEBUG_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
#endif
|
||||
|
||||
/* Finally, figure out the size of the DIMM */
|
||||
movl $0x0700, %ebx /* MC_BANK_CFG for 512MB */
|
||||
movl $0x10000000, %esi /* Offset: 256MB */
|
||||
|
||||
dimm_size_loop:
|
||||
movl $TEST_DATA1, 0 /* Write data to location 0 */
|
||||
movl $TEST_DATA2, (%esi) /* Write to memory size/2 */
|
||||
movl $0, 0x100 /* Clear the bus */
|
||||
movl 0, %eax /* Read data from location 0 */
|
||||
movl $0, 0 /* Clear location 0 */
|
||||
|
||||
cmpl $TEST_DATA1, %eax /* If no aliasing, we have found */
|
||||
je dimm_size_found /* out the memory size */
|
||||
|
||||
/* We had aliasing, so go to the next smaller setting */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl (%edi), %edx /* Get current MC_BANK_CFG settings */
|
||||
movl $~DIMM_SZ, %eax /* Mask for the DIMM size */
|
||||
roll %cl, %eax /* Shift for the right DIMM */
|
||||
and %eax, %edx /* Do the masking */
|
||||
decb %bh /* Halve the memory size */
|
||||
jc mem_sizing_failed /* Nothing matched, we've failed */
|
||||
shll %cl, %ebx /* Shift for the right DIMM */
|
||||
orl %ebx, %edx /* And merge it into the settings */
|
||||
shrl %cl, %ebx /* And shift it back again */
|
||||
shrl $1, %esi /* Divide test address by 2 */
|
||||
|
||||
movl %edx, (%edi) /* Use the new MC_BANK_CFG settings */
|
||||
CALLSP(do_refresh)
|
||||
jmp dimm_size_loop
|
||||
|
||||
dimm_size_found:
|
||||
/* Save the page size we found in EBP */
|
||||
movl $~DIMM_SZ, %eax
|
||||
roll %cl, %eax
|
||||
andl %eax, %ebp
|
||||
movl %ebx, %eax
|
||||
shll %cl, %eax
|
||||
or %eax, %ebp
|
||||
|
||||
shrl $16-1, %esi
|
||||
movw %si, %di
|
||||
movl %edx, %esi
|
||||
CONSOLE_INFO_TX_STRING($str_dimm_size)
|
||||
movw %di, %ax
|
||||
shll $16, %eax
|
||||
CONSOLE_INFO_TX_HEX32(%eax)
|
||||
CONSOLE_INFO_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
|
||||
next_dimm:
|
||||
movl $0x12345678, 0 /* Write garbage to location 0 */
|
||||
|
||||
addb $16, %cl
|
||||
movl $0x57400070, %edx /* No DIMM0, DIMM1 is maxed */
|
||||
|
||||
/* Try the two shift values 0, and 16 */
|
||||
cmpb $32, %cl
|
||||
jne dimm_loop
|
||||
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_done)
|
||||
CONSOLE_DEBUG_TX_HEX32(%ebp)
|
||||
CONSOLE_DEBUG_TX_STRING($str_nl)
|
||||
movl %esi, %edx
|
||||
|
||||
/* Finally use the MC_BANK_CFG settings we've calculated */
|
||||
movw $MC_BANK_CFG, %di
|
||||
movl %ebp, (%edi)
|
||||
|
||||
jmp ram_setup_end
|
||||
|
||||
mem_sizing_failed:
|
||||
#ifdef DEBUG
|
||||
movl %edx, %esi
|
||||
CONSOLE_DEBUG_TX_STRING($str_failed)
|
||||
movl %esi, %edx
|
||||
#endif
|
||||
movl $0xffff0000, %eax
|
||||
roll %cl, %eax
|
||||
andl %eax, %ebp
|
||||
movl $0x00000070, %eax
|
||||
shll %cl, %eax
|
||||
orl %eax, %ebp
|
||||
|
||||
jmp next_dimm
|
||||
|
||||
str_setup_default_memory:
|
||||
.string "Setting up default parameters for memory\r\n"
|
||||
str_sizing_memory:
|
||||
.string "Sizing memory\r\n"
|
||||
str_sizing_done:
|
||||
.string "Sizing done\r\n"
|
||||
str_done:
|
||||
.string "Memory sizing done, MC_BANK_CFG = 0x"
|
||||
str_probing:
|
||||
.string "Probing for DIMM"
|
||||
str_found:
|
||||
.string " Found DIMM"
|
||||
str_failed:
|
||||
.string " Failed to identify DIMM"
|
||||
str_page_size:
|
||||
.string " Page Size: "
|
||||
str_component_banks:
|
||||
.string " Component Banks: "
|
||||
str_module_banks:
|
||||
.string " Module Banks: "
|
||||
str_dimm_size:
|
||||
.string " DIMM size: "
|
||||
str_nl:
|
||||
.string "\r\n"
|
||||
|
||||
/**********************************************************************/
|
||||
/* all these functions assume that the upper word of EDI contains
|
||||
GX_BASE */
|
||||
|
||||
/* Destroys EAX, high word of ECX and low word of EDI */
|
||||
do_refresh:
|
||||
shll $16, %ecx /* save CX */
|
||||
movw $MC_MEM_CNTRL1, %di
|
||||
movl (%edi), %eax
|
||||
orb $RFSHTST, %al
|
||||
movw $NUM_REFRESH, %cx
|
||||
1: movl %eax, (%edi)
|
||||
loopw 1b
|
||||
andb $~RFSHTST, %al
|
||||
movl %eax, (%edi)
|
||||
shrl $16, %ecx /* restore CX */
|
||||
RETSP
|
||||
|
||||
enable_dimm:
|
||||
/* Start the SDCLK's */
|
||||
movw $MC_MEM_CNTRL1, %di
|
||||
movl (%edi), %eax
|
||||
andl $~SDCLKSTRT, %eax
|
||||
movl %eax, (%edi)
|
||||
orl $SDCLKSTRT, %eax
|
||||
movl %eax, (%edi)
|
||||
|
||||
/* Unmask the SDCLK's */
|
||||
movw $MC_MEM_CNTRL2, %di
|
||||
movl (%edi), %eax
|
||||
andl $~(SDCLK_MASK | SDCLKOUT_MASK), %eax
|
||||
movl %eax, (%edi)
|
||||
|
||||
movw $5000, %cx /* Wait for clocks to unmask */
|
||||
1: outb %al, $0xed
|
||||
loopw 1b
|
||||
|
||||
movw $MC_MEM_CNTRL1, %di /* Refresh memory */
|
||||
movl (%edi), %eax
|
||||
orb $RFSHTST, %al
|
||||
movw $NUM_REFRESH, %cx
|
||||
1: movl %eax, (%edi)
|
||||
loopw 1b
|
||||
andb $~RFSHTST, %al
|
||||
|
||||
/* Start the SDCLK's */
|
||||
andl $~PROGRAM_SDRAM, %eax
|
||||
movl %eax, (%edi)
|
||||
orl $PROGRAM_SDRAM | 0x00002000, %eax /* Set refresh timing */
|
||||
movl %eax, (%edi)
|
||||
andl $~PROGRAM_SDRAM, %eax
|
||||
movl %eax, (%edi)
|
||||
|
||||
movl (%edi), %eax /* Refresh memory again */
|
||||
orb $RFSHTST, %al
|
||||
movw $NUM_REFRESH, %cx
|
||||
1: movl %eax, (%edi)
|
||||
loopw 1b
|
||||
|
||||
movw $2000, %cx
|
||||
1: outb %al, $0xed
|
||||
loopw 1b
|
||||
|
||||
RETSP
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ram_setup_end:
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
End:
|
||||
*/
|
||||
|
|
@ -6,6 +6,27 @@
|
|||
void
|
||||
southbridge_fixup()
|
||||
{
|
||||
#if (CONFIG_LINUXBIOS_ENABLE_IDE == 1)
|
||||
struct pci_dev *pcidev;
|
||||
|
||||
printk_info( "Enabling IDE...");
|
||||
|
||||
pcidev = pci_find_device(0x8086, 0x7111, (void *)NULL);
|
||||
|
||||
if (! pcidev) {
|
||||
printk_err("Can't find piix4e\n");
|
||||
} else {
|
||||
unsigned char c;
|
||||
|
||||
pci_read_config_word(pcidev, 0x41, &c);
|
||||
c |= 0x80;
|
||||
pci_read_config_word(pcidev, 0x43, &c);
|
||||
c |= 0x80;
|
||||
printk_info("Enabled IDE for channels 1 and 2\n");
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
void nvram_on()
|
||||
|
|
|
|||
7
src/southbridge/nsc/cs5530/Config
Normal file
7
src/southbridge/nsc/cs5530/Config
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
# freebios/src/southbridge/nsc/cs5530/Config
|
||||
# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
# Config file for the National Semiconductor CS5530 southbridge
|
||||
# a.k.a. companion chip
|
||||
|
||||
object southbridge.o
|
||||
|
||||
92
src/southbridge/nsc/cs5530/southbridge.c
Normal file
92
src/southbridge/nsc/cs5530/southbridge.c
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
freebios/src/southbridge/nsc/cs5530/southbridge.c
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Configure the National Semiconductor CS5530 southbridge
|
||||
*/
|
||||
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <cpu/p5/io.h>
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#define NAME "cs5530: "
|
||||
|
||||
void nvram_on()
|
||||
{
|
||||
}
|
||||
|
||||
void final_southbridge_fixup()
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
u8 b;
|
||||
u16 int_map;
|
||||
int inta, intb, intc, intd;
|
||||
u16 trig;
|
||||
|
||||
printk_info("Final southbridge fixup\n");
|
||||
|
||||
dev = pci_find_device(PCI_VENDOR_ID_CYRIX,
|
||||
PCI_DEVICE_ID_CYRIX_5530_LEGACY,
|
||||
(void *)NULL);
|
||||
if (!dev) {
|
||||
printk_warning(NAME "Can't find PCI bridge\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pci_read_config_word(dev, 0x5c, &int_map);
|
||||
printk_debug("F0/5c: 0x%04x\n", int_map);
|
||||
inta = CS5530_INTA;
|
||||
intb = CS5530_INTB;
|
||||
intc = CS5530_INTC;
|
||||
intd = CS5530_INTD;
|
||||
printk_info(NAME "PCI INTA=%d, INTB=%d, INTC=%d, INTD=%d\n",
|
||||
inta, intb, intc, intd);
|
||||
int_map = inta | (intb<<4) | (intc<<8) | (intd<<12);
|
||||
pci_write_config_word(dev, 0x5c, int_map);
|
||||
|
||||
pci_read_config_word(dev, 0x5c, &int_map);
|
||||
printk_debug("F0/5c: 0x%04x\n", int_map);
|
||||
|
||||
/* All PCI interrupts are level trigged, the rest are edge trigged */
|
||||
printk_debug("4d0: 0x%02x\n", inb(0x4d0));
|
||||
printk_debug("4d1: 0x%02x\n", inb(0x4d1));
|
||||
trig = 0;
|
||||
if (inta) trig |= (1<<inta);
|
||||
if (intb) trig |= (1<<intb);
|
||||
if (intc) trig |= (1<<intc);
|
||||
if (intd) trig |= (1<<intd);
|
||||
outb(trig, 0x4d0);
|
||||
outb(trig >> 8, 0x4d1);
|
||||
printk_debug("4d0: 0x%02x\n", inb(0x4d0));
|
||||
printk_debug("4d1: 0x%02x\n", inb(0x4d1));
|
||||
|
||||
pci_read_config_byte(dev, 0x5b, &b);
|
||||
printk_debug("F0/5b = 0x%02x\n", b);
|
||||
#ifdef CS5530_PRIMARY_IDE
|
||||
printk_info(NAME "Enabling Primary IDE Controller\n");
|
||||
b |= 1<<3;
|
||||
#endif
|
||||
#ifdef CS5530_SECONDARY_IDE
|
||||
printk_info(NAME "Enabling Secondary IDE Controller\n");
|
||||
b |= 1<<4;
|
||||
#endif
|
||||
printk_debug("F0/5b = 0x%02x\n", b);
|
||||
pci_write_config_byte(dev, 0x5b, b);
|
||||
|
||||
dev = pci_find_slot(0, PCI_DEVFN(0x13, 0));
|
||||
if (dev) {
|
||||
printk_debug(NAME "USB is on INTA, IRQ %d\n", inta);
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, inta);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
c-basic-offset: 8
|
||||
End:
|
||||
*/
|
||||
4
src/southbridge/nsc/scx200/Config
Normal file
4
src/southbridge/nsc/scx200/Config
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# freebios/src/southbridge/nsc/scx200/Config
|
||||
# Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
object southbridge.o
|
||||
268
src/southbridge/nsc/scx200/scx200_setup.inc
Normal file
268
src/southbridge/nsc/scx200/scx200_setup.inc
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
freebios/src/northsouthbridge/NSC/scx200/chipset_setup.inc
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Do chipset setup for a National Semiconductor SCx200 CPU.
|
||||
*/
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
scx200_setup_start:
|
||||
/* Configure F0 */
|
||||
movl $f0_setup_table, %esi
|
||||
movl $f0_setup_len, %ecx
|
||||
movl $0x80009000, %ebx /* F0 Config Space */
|
||||
|
||||
f0_setup_loop:
|
||||
movb (%esi), %bl
|
||||
CALLSP(scx200_pci_read_config_byte)
|
||||
incl %esi
|
||||
andb (%esi), %al
|
||||
incl %esi
|
||||
orb (%esi), %al
|
||||
CALLSP(scx200_pci_write_config_byte)
|
||||
incl %esi
|
||||
loopl f0_setup_loop
|
||||
|
||||
/* Configure F5 */
|
||||
movl $f5_setup_table, %esi
|
||||
movl $f5_setup_len, %ecx
|
||||
movl $0x80009500, %ebx /* F5 Config Space */
|
||||
|
||||
f5_setup_loop:
|
||||
movb (%esi), %bl
|
||||
CALLSP(scx200_pci_read_config_byte)
|
||||
incl %esi
|
||||
andb (%esi), %al
|
||||
incl %esi
|
||||
orb (%esi), %al
|
||||
CALLSP(scx200_pci_write_config_byte)
|
||||
incl %esi
|
||||
loopl f5_setup_loop
|
||||
|
||||
/* Configure the SIO address */
|
||||
movw $0x6200, %dx /* I/O Control Register */
|
||||
inl %dx, %eax
|
||||
movl $0x0f040000, %eax /* SIO at 0x15c, Enable USB */
|
||||
outl %eax, %dx
|
||||
|
||||
movw $0x15c, %dx /* Super I/O */
|
||||
movb $0x20, %al /* Index 0x20, SIO Config */
|
||||
outb %al, %dx
|
||||
xorw $1, %dx
|
||||
inb %dx, %al
|
||||
cmpb $0xf5, %al /* SIO ID */
|
||||
jnz scx200_setup_start
|
||||
|
||||
config_block_setup:
|
||||
movw $0x2ea, %dx /* initial register to set address */
|
||||
movw $SCx200_CB_BASE, %ax /* Config Block Base Address */
|
||||
outw %ax, %dx
|
||||
|
||||
movw $SCx200_CB_BASE, %bx /* Config Block Base Address */
|
||||
movw %bx, %dx
|
||||
addw $0x30, %dx /* PMR */
|
||||
movl $SCx200_PMR, %eax
|
||||
outl %eax, %dx
|
||||
movw %bx, %dx
|
||||
addw $0x34, %dx /* MCR */
|
||||
movl $SCx200_MCR, %eax
|
||||
outl %eax, %dx
|
||||
movw %bx, %dx
|
||||
addw $0x12, %dx /* PPCR */
|
||||
inb %dx, %al
|
||||
andb $0xd1, %al /* Enable PLLs */
|
||||
outb %al, %dx
|
||||
|
||||
#if 0
|
||||
/* But this stops the serial port from working. */
|
||||
movw %bx, %dx
|
||||
addw $0x18, %dx /* PLL3 */
|
||||
movl $0x7601d004, %eax /* Must be programmed with this */
|
||||
outl %eax, %dx /* value according to databook */
|
||||
#endif
|
||||
|
||||
#ifdef WATCHDOG_INIT
|
||||
watchdog_setup:
|
||||
movw $SCx200_CB_BASE, %bx /* Config Block Base Address */
|
||||
movw %bx, %dx
|
||||
addw $0x2, %dx /* WDCNFG */
|
||||
movw $0xfa, %ax /* enable watchdog */
|
||||
outw %ax, %dx
|
||||
movw %bx, %dx /* WDTO */
|
||||
movw $32*(WATCHDOG_INIT), %ax
|
||||
outw %ax, %dx
|
||||
#endif
|
||||
|
||||
/* RTC setup */
|
||||
movw $0x70, %dx
|
||||
movb $0x0d, %al
|
||||
outb %al, %dx
|
||||
movw $0x71, %dx
|
||||
inb %dx, %al
|
||||
inb %dx, %al
|
||||
movw $0x70, %dx
|
||||
movb $0x0b, %al
|
||||
outb %al, %dx
|
||||
movw $0x71, %dx
|
||||
movb $0x02, %al
|
||||
outb %al, %dx
|
||||
|
||||
/* GPIO setup */
|
||||
/* FIXME ought to do GPIO setup here */
|
||||
|
||||
/* Configure the SIO itself */
|
||||
lea sio_setup_table, %esi
|
||||
movl $sio_setup_size, %ecx
|
||||
mov $0x15c, %dx
|
||||
|
||||
sio_setup_loop:
|
||||
movb (%esi), %al
|
||||
incl %esi
|
||||
outb %al, %dx
|
||||
xorb $1, %dl
|
||||
loop sio_setup_loop
|
||||
|
||||
jmp scx200_setup_end
|
||||
|
||||
scx200_pci_read_config_byte:
|
||||
movw $0xcf8, %dx
|
||||
movl %ebx, %eax
|
||||
outl %eax, %dx
|
||||
movw %ax, %dx
|
||||
andw $3, %dx
|
||||
orw $0xcfc, %dx
|
||||
inb %dx, %al
|
||||
RETSP
|
||||
|
||||
scx200_pci_write_config_byte:
|
||||
movw $0xcf8, %dx
|
||||
xchgl %ebx, %eax
|
||||
outl %eax, %dx
|
||||
movw %ax, %dx
|
||||
andw $3, %dx
|
||||
orw $0xcfc, %dx
|
||||
xchgl %ebx, %eax
|
||||
outb %al, %dx
|
||||
RETSP
|
||||
|
||||
f0_setup_table:
|
||||
.byte 0x10, 0x00, 0x01 /* F0BAR0/GPIO = 0x00006401 */
|
||||
.byte 0x11, 0x00, 0x64
|
||||
.byte 0x12, 0x00, 0x00
|
||||
.byte 0x13, 0x00, 0x00
|
||||
|
||||
.byte 0x47, 0xfb, 0x06 /* Enable F0BAR0/GPIO, F0BAR1/LPC */
|
||||
.byte 0x5a, 0x00, 0x01 /* Enable RTC Positive Decode */
|
||||
.byte 0x5b, 0x00, 0x01 /* Enable LPC Positive Decode */
|
||||
|
||||
#ifdef SCx200_DOCCS_BASE
|
||||
.byte 0x78, 0x00, (SCx200_DOCCS_BASE>>0)&0xff
|
||||
.byte 0x79, 0x00, (SCx200_DOCCS_BASE>>8)&0xff
|
||||
.byte 0x7a, 0x00, (SCx200_DOCCS_BASE>>16)&0xff
|
||||
.byte 0x7b, 0x00, (SCx200_DOCCS_BASE>>24)&0xff
|
||||
|
||||
.byte 0x7c, 0x00, (SCx200_DOCCS_CTRL>>0)&0xff
|
||||
.byte 0x7d, 0x00, (SCx200_DOCCS_CTRL>>8)&0xff
|
||||
.byte 0x7e, 0x00, (SCx200_DOCCS_CTRL>>16)&0xff
|
||||
.byte 0x7f, 0x00, (SCx200_DOCCS_CTRL>>24)&0xff
|
||||
#endif
|
||||
|
||||
.byte 0x43, 0xff, 0x80 /* Must be set to 1 */
|
||||
.byte 0x43, 0xfd, 0x00 /* Speed up PIT accesses */
|
||||
|
||||
f0_setup_len = (.-f0_setup_table) / 3
|
||||
|
||||
f5_setup_table:
|
||||
.byte 0x40, 0x00, 0xc1 /* F5BAR0 Mask = 0xffffffc1 */
|
||||
.byte 0x41, 0x00, 0xff
|
||||
.byte 0x42, 0x00, 0xff
|
||||
.byte 0x43, 0x00, 0xff
|
||||
|
||||
.byte 0x10, 0x00, 0x01 /* F5BAR0/X-Bus = 0x00006201 */
|
||||
.byte 0x11, 0x00, 0x62
|
||||
.byte 0x12, 0x00, 0x00
|
||||
.byte 0x13, 0x00, 0x00
|
||||
|
||||
.byte 0x04, 0x00, 0x03 /* Enable F5 Memory and I/O Space */
|
||||
f5_setup_len = (.-f5_setup_table) / 3
|
||||
|
||||
sio_setup_table:
|
||||
.byte 0x07, 0x00 /* Device 0 -- RTC */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x70, 0x08 /* Use IRQ 8 */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
|
||||
|
||||
.byte 0x07, 0x01 /* Device 1 -- System Wake-Up Ctrl */
|
||||
.byte 0x60, 0x08 /* I/O Base Address 0x860 */
|
||||
.byte 0x61, 0x60
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
|
||||
#ifdef SCx200_SP3_BASE
|
||||
.byte 0x07, 0x02 /* Device 2 -- Serial port 3 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_SP3_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_SP3_BASE&0xff
|
||||
.byte 0x70, SCx200_SP3_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SCx200_SP1_BASE
|
||||
.byte 0x07, 0x03 /* Device 3 -- Serial port 1 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_SP1_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_SP1_BASE&0xff
|
||||
.byte 0x70, SCx200_SP1_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SCx200_ACB1_BASE
|
||||
.byte 0x07, 0x05 /* Device 5 -- ACCESS.bus 1 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_ACB1_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_ACB1_BASE&0xff
|
||||
.byte 0x70, SCx200_ACB1_IRQ /* IRQ */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SCx200_ACB2_BASE
|
||||
.byte 0x07, 0x05 /* Device 6 -- ACCESS.bus 2 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_ACB2_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_ACB2_BASE&0xff
|
||||
.byte 0x70, SCx200_ACB2_IRQ /* IRQ */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SCx200_PP_BASE
|
||||
.byte 0x07, 0x08 /* Device 7 -- Parallel Port */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_PP_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_PP_BASE&0xff
|
||||
.byte 0x70, SCx200_PP_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SCx200_SP2_BASE
|
||||
.byte 0x07, 0x08 /* Device 8 -- Serial port 2 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SCx200_SP2_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SCx200_SP2_BASE&0xff
|
||||
.byte 0x70, SCx200_SP2_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
sio_setup_size = .-sio_setup_table
|
||||
|
||||
scx200_setup_end:
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/nano/bios/nano"
|
||||
End:
|
||||
*/
|
||||
95
src/southbridge/nsc/scx200/southbridge.c
Normal file
95
src/southbridge/nsc/scx200/southbridge.c
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
freebios/src/southbridge/nsc/scx200/southbridge.c
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Configure the National Semiconductor SCx200 southbridge. This
|
||||
chip is mostly the same as the CS5530 southbridge, but enough
|
||||
things are different to warrant two different files.
|
||||
*/
|
||||
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <cpu/p5/io.h>
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#define NAME "scx200: "
|
||||
|
||||
void nvram_on()
|
||||
{
|
||||
}
|
||||
|
||||
void final_southbridge_fixup()
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
u8 b;
|
||||
u16 int_map;
|
||||
int inta, intb, intc, intd;
|
||||
u16 trig;
|
||||
|
||||
printk_info("Final southbridge fixup\n");
|
||||
|
||||
dev = pci_find_device(PCI_VENDOR_ID_NS,
|
||||
PCI_DEVICE_ID_NS_SCx200_BRIDGE,
|
||||
(void *)NULL);
|
||||
if (!dev) {
|
||||
printk_warning(NAME "Can't find PCI bridge\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pci_read_config_word(dev, 0x5c, &int_map);
|
||||
printk_debug("F0/5c: 0x%04x\n", int_map);
|
||||
inta = SCx200_INTA;
|
||||
intb = SCx200_INTB;
|
||||
intc = SCx200_INTC;
|
||||
intd = SCx200_INTD;
|
||||
printk_info(NAME "PCI INTA=%d, INTB=%d, INTC=%d, INTD=%d\n",
|
||||
inta, intb, intc, intd);
|
||||
int_map = inta | (intb<<4) | (intc<<8) | (intd<<12);
|
||||
pci_write_config_word(dev, 0x5c, int_map);
|
||||
|
||||
pci_read_config_word(dev, 0x5c, &int_map);
|
||||
printk_debug("F0/5c: 0x%04x\n", int_map);
|
||||
|
||||
/* All PCI interrupts are level trigged, the rest are edge trigged */
|
||||
printk_debug("4d0: 0x%02x\n", inb(0x4d0));
|
||||
printk_debug("4d1: 0x%02x\n", inb(0x4d1));
|
||||
trig = 0;
|
||||
if (inta) trig |= (1<<inta);
|
||||
if (intb) trig |= (1<<intb);
|
||||
if (intc) trig |= (1<<intc);
|
||||
if (intd) trig |= (1<<intd);
|
||||
outb(trig, 0x4d0);
|
||||
outb(trig >> 8, 0x4d1);
|
||||
printk_debug("4d0: 0x%02x\n", inb(0x4d0));
|
||||
printk_debug("4d1: 0x%02x\n", inb(0x4d1));
|
||||
|
||||
pci_read_config_byte(dev, 0x5b, &b);
|
||||
printk_debug("F0/5b = 0x%02x\n", b);
|
||||
#ifdef SCx200_PRIMARY_IDE
|
||||
printk_info(NAME "Enabling Primary IDE Controller\n");
|
||||
b |= 1<<3;
|
||||
#endif
|
||||
#ifdef SCx200_SECONDARY_IDE
|
||||
printk_info(NAME "Enabling Secondary IDE Controller\n");
|
||||
b |= 1<<4;
|
||||
#endif
|
||||
printk_debug("F0/5b = 0x%02x\n", b);
|
||||
pci_write_config_byte(dev, 0x5b, b);
|
||||
|
||||
dev = pci_find_slot(0, PCI_DEVFN(0x13, 0));
|
||||
if (dev) {
|
||||
printk_debug(NAME "USB is on INTD, IRQ %d\n", intd);
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 4);
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, intd);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/nano"
|
||||
c-basic-offset: 8
|
||||
End:
|
||||
*/
|
||||
145
src/superio/NSC/pc97317/sio_setup.inc
Normal file
145
src/superio/NSC/pc97317/sio_setup.inc
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
freebios/src/superio/NSC/pc97317/sio_setup.inc
|
||||
|
||||
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
|
||||
|
||||
Set up a National Semiconductor PC97317 Super I/O
|
||||
*/
|
||||
|
||||
#ifndef SIO_BASE
|
||||
#define SIO_BASE 0x2e
|
||||
#endif
|
||||
|
||||
sio_boot:
|
||||
lea sio_boot_table, %esi
|
||||
movl $sio_boot_size, %ecx
|
||||
movw $SIO_BASE, %dx
|
||||
|
||||
sio_boot_loop:
|
||||
movb (%esi), %al
|
||||
incl %esi
|
||||
outb %al, %dx
|
||||
xorb $1, %dl
|
||||
loop sio_boot_loop
|
||||
|
||||
sio_rtc_boot:
|
||||
movb $0x0a, %al /* RTC Control Register A */
|
||||
outb %al, $0x70 /* RTC */
|
||||
inb $0x71, %al
|
||||
andb $0xf0, %al
|
||||
orb $0x06, %al /* Interrupt rate */
|
||||
outb %al, $0x71
|
||||
|
||||
sio_wakeup:
|
||||
movb $0x03, %al /* Use on chip clock multiplier */
|
||||
outb %al, $0xe8
|
||||
inb $0xe9, %al
|
||||
orb $0x07, %al
|
||||
outb %al, $0xe9
|
||||
|
||||
sio_wakeup_wait:
|
||||
inb $0xe9, %al /* Wait for the clock to stabilize */
|
||||
testb $0x80, %al
|
||||
jz sio_wakeup_wait
|
||||
|
||||
sio_setup:
|
||||
lea sio_setup_table, %esi
|
||||
movl $sio_setup_size, %ecx
|
||||
mov $SIO_BASE, %dx
|
||||
|
||||
sio_setup_loop:
|
||||
movb (%esi), %al
|
||||
incl %esi
|
||||
outb %al, %dx
|
||||
xorb $1, %dl
|
||||
loop sio_setup_loop
|
||||
|
||||
sio_rtc_setup:
|
||||
movb $0x0a, %al /* RTC Control Register A */
|
||||
outb %al, $0x70
|
||||
movb $0x26, %al /* Normal operation */
|
||||
outb %al, $0x71
|
||||
|
||||
movw $0x70, %dx
|
||||
movb $0x0d, %al
|
||||
outb %al, %dx
|
||||
movw $0x71, %dx
|
||||
inb %dx, %al
|
||||
inb %dx, %al
|
||||
movw $0x70, %dx
|
||||
movb $0x0b, %al
|
||||
outb %al, %dx
|
||||
movw $0x71, %dx
|
||||
movb $0x02, %al
|
||||
outb %al, %dx
|
||||
|
||||
jmp sio_setup_end
|
||||
|
||||
sio_boot_table:
|
||||
.byte 0x07, 0x08 /* LDN 8 -- Power Management */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, 0x00 /* Base High */
|
||||
.byte 0x61, 0xe8 /* Base Low */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
sio_boot_size = .-sio_boot_table
|
||||
|
||||
sio_setup_table:
|
||||
.byte 0x07, 0x00 /* Device 0 -- Keyboard */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x70, 0x01 /* IRQ 1 */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
|
||||
.byte 0x07, 0x02 /* Device 2 -- RTC & APC */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x70, 0x08 /* IRQ 8 */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
|
||||
#ifdef SIO_PP_BASE
|
||||
.byte 0x07, 0x04 /* Device 4 -- Parallel Port */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SIO_PP_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SIO_PP_BASE&0xff
|
||||
.byte 0x70, SIO_PP_IRQ /* IRQ */
|
||||
.byte 0xf0, 0xf2 /* PP Configuration, ECP, enabled */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SIO_SP2_BASE
|
||||
.byte 0x07, 0x05 /* Device 5 -- Serial port 2 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SIO_SP2_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SIO_SP2_BASE&0xff
|
||||
.byte 0x70, SIO_SP2_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SIO_SP1_BASE
|
||||
.byte 0x07, 0x06 /* Device 6 -- Serial port 1 */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SIO_SP1_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SIO_SP1_BASE&0xff
|
||||
.byte 0x70, SIO_SP1_IRQ /* IRQ */
|
||||
.byte 0xf0, 0x82 /* Serial Configuration Register */
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
#ifdef SIO_GPIO_BASE
|
||||
.byte 0x07, 0x07 /* Device 7 -- GPIO Ports */
|
||||
.byte 0x30, 0x00 /* Disable */
|
||||
.byte 0x60, SIO_GPIO_BASE>>8 /* I/O Base Address */
|
||||
.byte 0x61, SIO_GPIO_BASE&0xff
|
||||
.byte 0x30, 0x01 /* Enable */
|
||||
#endif
|
||||
|
||||
sio_setup_size = .-sio_setup_table
|
||||
|
||||
sio_setup_end:
|
||||
nop
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
compile-command: "make -C /export/bios/voyager2"
|
||||
c-basic-offset: 8
|
||||
End:
|
||||
*/
|
||||
1
src/superio/NSC/pc97317/superio.c
Normal file
1
src/superio/NSC/pc97317/superio.c
Normal file
|
|
@ -0,0 +1 @@
|
|||
|
||||
Loading…
Add table
Add a link
Reference in a new issue