Microcode released on August 29.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus with E0 step
Change-Id: Icf90b2fb3c70b1edae4979f8e491fe98a6766e95
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209465
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214843
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
With the latest changes to include stack storage within ramstage, we no longer
need to define Kconfig options for ramstage/exception stacks in arm64.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel on ryu
Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214607
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214777
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Optionally bring up secondary cpu according to devicetree.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and enabled bringing up second core on ryu.
Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214776
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214774
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
No need to pass in the same value for the ttb after just
calling mmu_init(). All current users are setting this once
and forgetting it.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214772
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.
Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214661
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209462
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209468
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209429
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
some clock gating and pcie settings are missed in original code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/214568
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the
trust zone. Rest of the TZ memory can be used by el3 monitor.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and boots to kernel
Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214370
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log
Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This macro is incorrect and should be counting by dword instead of byte.
The effects of this were subtle: incorrect events in ELOG and hanging when
waking from USB input because PME_B0 was not disabled properly.
BUG=chrome-os-partner:31611
BRANCH=none
TEST=test wake from suspend with USB keyboard
Change-Id: I7caf1d46283071787550a9765703897181774957
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214258
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU
BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus
Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214024
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This can be shared between mainboards, they are still free
to override if needed.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus
Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
core up out of reset.
Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213850
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original code won't set power gating for disabled port correctly,
due to it must be set before Lock
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify bit 24, 26 is set in RCBA(0x3a84) for samus
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab
Reviewed-on: https://chromium-review.googlesource.com/213561
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Instead of requiring the mainboards to know the magic
literals for the bus numbers provide an easier name to
number to handle all the weird ordering.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213491
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The existing cpu_reset does board-wide reset, thus, should be renamed.
BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Reviewed-on: https://chromium-review.googlesource.com/212982
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
fixed a coding error and sync sata configuration with ref code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/213137
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212795
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to access secure device register space the cpu
needs to have the page tables marked as secure memory. In
addition the page tables need to live within secure memory
otherwise the accesses default to non-secure.
Therefore move the page tables to the trustzone region. Remove
the TTB_* config options as well as removing the TTB reservations
from coreboot's resource list.
BUG=chrome-os-partner:31355
BUG=chrome-os-partner:31356
BRANCH=None
CQ-DEPEND=CL:213140
TEST=Built and booted into kernel.
Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213141
I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.
BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK
Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212887
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.
BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.
Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.
I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.
Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212671
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This was a merge error when I was pulling in some of the
code into this file I put it after the read of CAP2 but
before it is modified and written back. In the end the
DEVSLP bits are getting set/cleared that need to but the
other bits in the register may be wrong. Also when enabling
devslp set the devslp-present bit in each enabled port.
Also remove much of the 0:1f.2@0x98 setup and the attempt
to write (the write once) CAP register that is already
being written in the reference code.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212308
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212332
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211039
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The clk_rst.h file wasn't including files that had
functionality it was using resulting in broken builds
if just this file was included.
BUG=None
BRANCH=None
TEST=Built with just this file included -> no more errors.
Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212331
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Make sure the array size matches the number of supported
FUNITs. Also remove the FUNIT_NONE enumeration so that
there isn't an empty slot in the array at index 0.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built when array wasn't large enough. Compiler threw an error.
Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212330
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
To provide easier access to the base addresses of the controllers
by funit identifier add the base addresses to the data structure.
BUG=chrome-os-partner:31251
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built.
Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212169
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212168
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to prepare for USB initialization move the clock
configuration into a separate routine in the funit library.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted into recovery mode.
Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212167
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Just use direct pointers to the registers in the pre-filled
data structures. In 64-bit the sizes increase, but it's small.
The fields now directly point to the correct register so no
need to do any arithmetic to identify the correct register.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted on ryu into recovery.
Change-Id: I186bf5d145437472126067960e62d7ed6a25f295
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212166
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and ran on ryu through depthcharge into recovery mode.
Change-Id: I76fa8f1c3469b049df7f5bf943701ce18deeb927
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212151
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfuily for nyan, big and blaze
Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211200
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212161
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The high address field was being shifted in the wrong direction
resulting in the lower 12 bits of the upper address being dropped.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Was able to run on ryu and not hang while wiping memory.
Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211941
Reviewed-by: Tom Warren <twarren@nvidia.com>
