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broadwell: sata updates from 2.1.0 ref code

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fixed a coding error and sync sata configuration with ref code

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
     verify registers between samus and crb

Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/213137
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kane Chen 2014-08-19 10:51:46 -07:00 • committed by chrome-internal-fetch
commit 0fbb59e3c5
1 changed files with 8 additions and 14 deletions
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22
src/soc/intel/broadwell/sata.c
View file

@ -59,19 +59,8 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
/* Set timings */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92);
@ -81,7 +70,7 @@ static void sata_init(struct device *dev)
udelay(2);
/* Setup register 98h */
reg32 = pci_read_config16(dev, 0x98);
reg32 = pci_read_config32(dev, 0x98);
reg32 &= ~((1 << 31) | (1 << 30));
reg32 |= 1 << 23;
reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
@ -211,6 +200,11 @@ static void sata_init(struct device *dev)
reg32 |= (1 << 17) | (1 << 16) | (1 << 19);
reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
pci_write_config32(dev, 0x300, reg32);
/* Register Lock */
reg32 = pci_read_config32(dev, 0x9c);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x9c, reg32);
}
/*