coreboot: rk3288: add media

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209468
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
This commit is contained in:
huang lin 2014-07-30 10:58:37 -07:00 committed by chrome-internal-fetch
commit a30378a315
2 changed files with 11 additions and 2 deletions

View file

@ -31,12 +31,12 @@ bootblock-y += spi.c
romstage-y += cbmem.c
romstage-y += timer.c
romstage-y += monotonic_timer.c
romstage-y += media.c
ifeq ($(CONFIG_EARLY_CONSOLE),y)
romstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
endif
romstage-y += clock.c
romstage-y += spi.c
romstage-y += media.c
ramstage-y += cbmem.c
ramstage-y += timer.c

View file

@ -20,8 +20,17 @@
#include <cbfs.h>
#include <string.h>
#include <console/console.h>
#include "soc/rockchip/rk3288/spi.h"
int init_default_cbfs_media(struct cbfs_media *media)
{
return 0;
#if defined(__BOOT_BLOCK__)
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
CONFIG_CBFS_SRAM_CACHE_SIZE);
#else
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_DRAM_CACHE_ADDRESS,
CONFIG_CBFS_DRAM_CACHE_SIZE);
#endif
}