erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Nyans: replace cpu_reset with hard_reset

Browse source 
The existing cpu_reset does board-wide reset, thus, should be renamed.

BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Reviewed-on: https://chromium-review.googlesource.com/212982
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
This commit is contained in:
Daisuke Nojiri 2014-08-15 17:07:39 -07:00 • committed by chrome-internal-fetch
commit 29753b9c1d
17 changed files with 23 additions and 97 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/google/nyan/Makefile.inc
View file

@ -36,5 +36,6 @@ romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c

4
src/mainboard/google/nyan/pmic.c
View file

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (delay)
udelay(500);

5
src/mainboard/google/nyan/reset.c
View file

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan/reset.h
View file

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan/romstage.c
View file

@ -26,7 +26,7 @@
#include <cbmem.h>
#include <console/cbmem_console.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h"
@ -188,7 +188,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/mainboard/google/nyan_big/Makefile.inc
View file

@ -35,5 +35,6 @@ romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c

4
src/mainboard/google/nyan_big/pmic.c
View file

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (delay)
udelay(500);

5
src/mainboard/google/nyan_big/reset.c
View file

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan_big/reset.h
View file

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan_big/romstage.c
View file

@ -26,7 +26,7 @@
#include <cbmem.h>
#include <console/cbmem_console.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h"
@ -188,7 +188,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/mainboard/google/nyan_blaze/Makefile.inc
View file

@ -38,5 +38,6 @@ romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c

4
src/mainboard/google/nyan_blaze/pmic.c
View file

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (delay)
udelay(500);

5
src/mainboard/google/nyan_blaze/reset.c
View file

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan_blaze/reset.h
View file

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan_blaze/romstage.c
View file

@ -26,7 +26,7 @@
#include <cbmem.h>
#include <console/cbmem_console.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h"
@ -188,7 +188,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/soc/nvidia/tegra124/Kconfig
View file

@ -3,6 +3,7 @@ config SOC_NVIDIA_TEGRA124
default n
select HAVE_UART_MEMORY_MAPPED
select HAVE_UART_SPECIAL
select HAVE_HARD_RESET
select BOOTBLOCK_CONSOLE
select EARLY_CONSOLE
select DYNAMIC_CBMEM

2
src/vendorcode/google/chromeos/vboot_main.c
View file

@ -109,7 +109,7 @@ int vb2ex_read_resource(struct vb2_context *ctx,
static void reboot(void)
{
cpu_reset();
hard_reset();
}
static void recovery(void)