Aaron Durbin 813b0a8b3f tegra132: support GIC secondary cpu support ... For the secondary CPUs the set of banked registers needs to be initialized. In the boot CPU path all both the CPU's banked registers and the global register set is initialized. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu in kernel. Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/214774 Reviewed-by: Furquan Shaikh <furquan@chromium.org>		2014-08-29 03:10:42 +00:00
..
intel	broadwell: pcie updates from 2.1.0 ref code	2014-08-28 04:23:54 +00:00
nvidia	tegra132: support GIC secondary cpu support	2014-08-29 03:10:42 +00:00
qualcomm	ipq806x: implement GPIO API	2014-07-30 23:40:58 +00:00
rockchip	coreboot: rk3288: add gpio	2014-08-28 20:12:56 +00:00
samsung	coreboot classes: Add dynamic classes to coreboot	2014-07-28 19:19:34 +00:00
Kconfig	coreboot: rk3288: Add a stub implementation of the rk3288 SOC	2014-07-23 06:46:35 +00:00
Makefile.inc	coreboot: rk3288: Add a stub implementation of the rk3288 SOC	2014-07-23 06:46:35 +00:00