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tegra132: allow mainboards to insert memory regions in address map

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Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.

BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.

Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212161
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Aaron Durbin 2014-08-12 17:50:53 -05:00 • committed by chrome-internal-fetch
commit 8834256288
2 changed files with 26 additions and 13 deletions
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8
src/soc/nvidia/tegra132/include/soc/addressmap.h
View file

@ -100,6 +100,14 @@ enum {
/* Provided the careout id, obtain the base and size in 1MiB units. */
void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib);
/*
* Add any board-specific memory ranges to the address map when executing
* on aarchv8 core.
*/
struct memranges;
void mainboard_add_memory_ranges(struct memranges *map);
/*
* There are complications accessing the Trust Zone carveout region. The
* AVP cannot access these registers and the CPU can't access this register

31
src/soc/nvidia/tegra132/mmu_operations.c
View file

@ -44,39 +44,44 @@ static void print_memranges(struct memranges *mmap_ranges)
}
static void tegra132_memrange_init(void)
static void tegra132_memrange_init(struct memranges *map)
{
uint64_t start,end;
const unsigned long devmem = MA_DEV | MA_NS | MA_RW;
const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW;
memranges_init_empty(&t132_mmap_ranges);
memranges_init_empty(map);
memory_in_range_below_4gb(&start,&end);
/* Device memory below DRAM */
memranges_insert(&t132_mmap_ranges, 0, start * MiB, MA_DEV | MA_NS |
MA_RW);
memranges_insert(map, 0, start * MiB, devmem);
/* DRAM */
memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
MA_MEM | MA_NS | MA_RW);
memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem);
memory_in_range_above_4gb(&start,&end);
memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
MA_MEM | MA_NS | MA_RW);
memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem);
/* SRAM */
memranges_insert(&t132_mmap_ranges, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE,
MA_MEM | MA_NS | MA_RW);
memranges_insert(map, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, cachedmem);
}
print_memranges(&t132_mmap_ranges);
void __attribute__((weak)) mainboard_add_memory_ranges(struct memranges *map)
{
/* Don't add any ranges by default. */
}
void tegra132_mmu_init(void)
{
uint64_t *ttb_buffer = (uint64_t*)CONFIG_TTB_BUFFER;
uint64_t ttb_size = (uint64_t)CONFIG_TTB_SIZE;
tegra132_memrange_init();
mmu_init(&t132_mmap_ranges,ttb_buffer,ttb_size);
struct memranges *map = &t132_mmap_ranges;
tegra132_memrange_init(map);
mainboard_add_memory_ranges(map);
print_memranges(map);
mmu_init(map,ttb_buffer,ttb_size);
mmu_enable((uint64_t)ttb_buffer);
}