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broadwell: Changes from 2.2.0 ref code

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- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU

BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus

Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214024
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-08-25 10:14:08 -07:00 • committed by chrome-internal-fetch
commit 5d166a0c4d
2 changed files with 12 additions and 2 deletions
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7
src/soc/intel/broadwell/cpu.c
View file

@ -247,8 +247,11 @@ static void initialize_vr_config(void)
msr = rdmsr(MSR_VR_MISC_CONFIG2);
msr.lo &= ~0xffff;
/* Allow CPU to control minimum voltage completely (15:8) and
* set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
msr.lo |= 0x006f;
* set the fast ramp voltage in 10mV steps. */
if (cpu_family_model() == BROADWELL_FAMILY_ULT)
msr.lo |= 0x006a; /* 1.56V */
else
msr.lo |= 0x006f; /* 1.60V */
wrmsr(MSR_VR_MISC_CONFIG2, msr);
}

7
src/soc/intel/broadwell/sata.c
View file

@ -91,6 +91,13 @@ static void sata_init(struct device *dev)
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
(void) read32(abar + 0x0c); /* Read back 1 */