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broadwell: fixed power gating enable for disabled sata port

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The original code won't set power gating for disabled port correctly,
due to it must be set before Lock

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
     verify bit 24, 26 is set in RCBA(0x3a84) for samus
Signed-off-by: Kane Chen <kane.chen@intel.com>

Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab
Reviewed-on: https://chromium-review.googlesource.com/213561
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
This commit is contained in:
Kane Chen 2014-08-21 10:36:17 -07:00 • committed by chrome-internal-fetch
commit 066c8c81df
2 changed files with 3 additions and 2 deletions
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3
src/soc/intel/broadwell/finalize.c
View file

@ -100,6 +100,9 @@ static void broadwell_finalize(void *unused)
reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
/* Read+Write the following registers */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);

2
src/soc/intel/broadwell/lpc.c
View file

@ -347,8 +347,6 @@ static void pch_pm_init(struct device *dev)
if (RCBA32(FD) & PCH_DISABLE_ADSPD)
RCBA32_OR(0x2b1c, (1 << 29));
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
}
static void pch_cg_init(device_t dev)