Replace the magic number 0x00000001 with the BIT(0) macro for
QCLIB_GA_ENABLE_UART_LOGGING. This improves readability and
maintainability by clearly indicating that a specific bit is being set.
TEST=Able to build google/herobrine.
Change-Id: Ie425a68c6721343ca53eb883d6278decca92bcad
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set PL4 to the wattage of the included AC adapter. The EC will override
this limit at runtime, if necessary (for example, if a weaker USB-PD
power supply is connected).
PsysPmax is set according to the board schematics (RPsys resistor),
which ensures that the Psys signal generated by the battery charger and
interpreted by SOC VRs is interpreted correctly and that Psys power
limits applied by the EC work as expected.
Change-Id: I56e9c20556553940c308150f7e470628f56c3991
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The DDI lane number in `enum ddi_ports` is 1-based, while the TCPx
display link numbers from the SoC are 0 based. Fix the off-by-one error
and set the HDMI DDI lane index to the correct value of 3.
Change-Id: I861e58150ebe8b97cf3e9be81c2bd5494eff600b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86751
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, to make sure that the UEFI setup menu stays legible on HiDPI
displays, the VBT has the Fixed Display feature enabled with the
resolution set to 1920x1200.
If the secondary display feature is also enabled, and a monitor with
resolution lower than 1920x1200 is connected, the result is that neither
the internal nor external display is initialized.
Disable the secondary display feature to ensure that the internal
display keeps working regardless of any connected external displays.
Change-Id: I47630f5ce9573ed0ae86621252a04d41a92d40cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86713
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Split V5x0TU into a separate variant of the mtl-h baseboard. This is in
preparation to add support for the V5x0TNx variants, which is a
different variant of the board, with a discrete NVIDIA GPU.
Change-Id: I4f8215ace6b7a394f8d196be3f81c33b2cb4e9ec
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86709
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set TCSS SOC Aux orientation override as per the mainboard schematic.
Change-Id: I45903f26a3f724e6bd82645b0fe3d1e919a84833
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86697
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all USB configuration from the parent SOC node to the appropriate
XHCI controller device nodes in the devicetree.
Change-Id: Ib702b132698bcb71b4e7b6fa51c6a428bfe77252
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Probing the clock request signal is not required on this board and with
the SSD models the board is sold with.
Change-Id: I51b0d0f2b390912cf8fff45d736e317de31863ed
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Riven cannot boot into OS from 2nd source eMMC, show message
"Something went wrong booting from internal disk" and stop in depthcharge.
According to Intel provides eMMC DLL delay patch that tuning on each
riven different eMMC system to modify eMMC DLL tuning value to improve initialization reliability.
BUG=b:401663746
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Ib36650f2a8fca486c8c89fb9f2ef42452b7a4cfa
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86778
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.
Change-Id: I95ab68d1b5bb73738b5b6f9461d2b7771e75f17a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The MTL FSP headers in github do not include FirmwareVersionInfo.h, so
DISPLAY_FSP_VERSION_INFO_2 needs to be deselected when using FSP
binaries from the repo.
TEST=tested with subsequent patch
Change-Id: I53dae842f545b3d4fe34ded57916f33716777a7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate SPD id for Nanya memory NT6AP512T32BL-J1
BUG=b:401424949
TEST=go run ./util/spd_tools/src/part_id_gen/part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/drawcia/memory/ \
src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
Change-Id: Icb1a6894307bd27c7d5ea25adb6cf0c8514c661c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86764
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refine dptx_get_edid function to read extension edid to bring up 2.8k
120hz OLED panel.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
EQ training pass
Change-Id: If35782950ae02d892ea697580fa4991595c21533
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DisplayID 2.0 extension. Right now, the implementation
only supports 'Type VII – Detailed timing' data block decoding.
Reference: 'DisplayID v2.1a.pdf'
BUG=b:392040003
BRANCH=rauru
TEST=Check FW screen on a panel than supports Display ID 2.0
Change-Id: I1b8a5ab3ada5c8eacc7b6dde3d33ec72b3790960
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to E-EDID A.2_revised_2020.pdf, block maps are optional in
EDID 1.4. If block maps are used then 254 is the maximum number.
Otherwise, 255 is the maximum number. For now, we simply print the
number of extension blocks.
BUG=b:392040003
BRANCH=rauru
TEST=Verify with the panel containing two EDID extension blocks
Change-Id: I2458e3493e74f91af6422b36285bb95e438a29f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Allow a board to use the default turbo ratio by not specifying
turbo_ratio_limit and turbo_ratio_limit_cores in the devicetree.cb.
TEST: Intel PTAT tool no longer complains about 0Mhz turbo frequency.
Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch updates the TCH_PAD_INT_N GPP from A13 to F18
The Touch Pad's interrupt line (TCH_PAD_INT_N) was previously connected
to GPP_A13, This patch moves the interrupt line to GPP_F18, aligning it
with the THC1-i2c interface.
Both LPSS-i2c and THC1-i2c share SCL/SDA signals, with the exception of
the interrupt pin. This change ensures the interrupt pin shared between
both the interface.
The Tier-1 PMC GPE programming specifications limit us to configuring
three GPIO banks. Currently, GPP_A, GPP_D, and GPP_E are utilized, as
demonstrated in
[https://github.com/coreboot/coreboot/blob/main/src/mainboard/google/
fatcat/variants/baseboard/fatcat/devicetree.cb#L3]
We encounter a constraint when attempting to add GPP_F as an additional
Tier-1 GPIO due to the exhaustion of available PMC configuration
registers. However, the THC touchpad requires wake-capable registration,
necessitating a PMC GPE entry.
To resolve this, we have opted to configure GPP_F18 as an IOAPIC
interrupt. This solution provides a dedicated pin, avoiding the
complexities of GPIO shared IRQ masking. Furthermore, GPP_F18 supports
both interrupt (IRQ) and wake functionality, as defined by the ACPI
ACPI_IRQ_WAKE_LEVEL_LOW entry.
Snippet of change in runtime ASL code:
w/o cl:
`Name (_S0W, 0x03) // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x0D,
0x03
})`
w/ cl: no such entry
This patch also removed the GPP_F18 entry from the finger print sensor
config to avoid conflicts.
BUG=b:395160736
TEST=able to build google/fatcat. Verfied touchpad functionality
Change-Id: Ied917427225035a484a5873fa734f4c9f14277c0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Disable smart card reader power saving as W/A to avoid detect issue
BUG=b:383375529
TEST=Check whether the smart card reader exists without a card inserted
localhost~# lsusb
Bus 004 Device 009: ID 2cb7:0007 Fibocom Wireless Inc. L850-GL
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 010: ID 058f:9540 Alcor Micro Corp. AU9540 Smartcard Reader
Bus 003 Device 002: ID 0408:5479 Quanta Computer, Inc. HP 5M Camera
Bus 003 Device 012: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 003 Device 004: ID 8087:0033 Intel Corp.
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Change-Id: Idfff67b8fadd2ca07572fb3dad8bdffbbf7acad0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select FSP_TYPE_IOT, so that Nissa-baseboard boards can be built using
FSP binaries from 3rdparty/fsp.
TEST=build/boot google/craask
Change-Id: I0ba45205e3af9daf7c41d393689d8f14d847a446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Drop duplicate/unused `mclk` field, which corrects the size of the SSDB
struct to 108 bytes. Size/fields confirmed by comparing to DSDT
dumps of UEFI firmware and SSDB struct in linux MIPI driver (ref:
/include/media/ipu-bridge.h).
Change-Id: Iea5b2138d2396e32bcecb3a48ab2b159a9b33345
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add more platform type values. Values sourced from Slimbootloader and
various DSDT dumps on github.
Change-Id: If7ea46aad76dfedf89f764e60d9bf6061f53cbe1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86794
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards use BootGuard, which isn't fully working in coreboot as
it requires the bootblock to be relocatable.
Turn off the PMC to workaround the missing BootGuard requirements, so
that they will turn on when pressing the power button.
Change-Id: Idd03684d9fb4573fc160e17ac2c28c39bc8b2ddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The _STA method of redrix i2c3's power resource currently always returns
true. This causes the device to be powered on by the kernel in a boot
critical path (in acpi_bus_init_power) and blocks it for 300ms due to
the sleep in the _ON method. To prevent this sleep from blocking the
boot, enable use_gpio_for_status so that the implementation of _STA
returns the device's actual power state and the kernel powers on the
device in another place that doesn't block boot.
BUG=b:397355818
TEST=Boot the device, confirm that kernel doesn't sleep for 300ms during
acpi_bus_init_power and the touchscreen works without any problems.
Change-Id: I517a9477f7b59b621337c56eedbfcf17b82dc39b
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86749
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _STA method of drivers/i2c/generic PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_i2c_generic_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].
[1] https://review.coreboot.org/c/coreboot/+/55027
BUG=b:397355818
TEST=Dump SSDT on redrix with CB:86749
Change-Id: I5c0a423730788d634a780d1d1d8c87a7007cc150
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: I350af852ffed5afda4bbc5a85f5b9db035a99995
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86785
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.
Change-Id: I4dae9ff95d448924f1c2a199053be1ad0ca1cece
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86784
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The entry only provided CNVi configuration, and this board does not
use CNVi, so this entry is not required.
Change-Id: I737bed22f5d1545fe91e37d8e55c7c43d1d841fd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 3a8835f0e8 ("mb/starlabs/*: Unify tcc_offset settings")
unified the TCC offsets based on:
* 70, 80 and 90 degrees for fanless boards
* 80, 90 and 100 degrees for fanned boards
This board has a fan, so make it follow the above.
Change-Id: Ic40ec1a317c787cf7695b37246b2cb337043af2d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.
Change-Id: Ibcafae6b9bf495e3d41e3a2c49cda070db1c2e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: Ie3fe24be948b256b47eb8d48fd8a84d6daa2702f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86742
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_F18 is currently shared between the fingerprint sensor GSPI0-CS and
the touchpad THC1-INT.
This commit moves the FPS GSPI0-CS signal to GPP_E17, which is a GSPI-0
CS alternative option and moves the current GSPI0A-CS pin GPP_F18 to
not connected.
Schematic version dated march'25 has the rework details.
BUG=b:395147436
TEST=Build and boot google/fatcat. Able to fetch the FPS version using
`ectool --name=cros_fp version`
Change-Id: I1131962e9b6423bbf68fb92189b8910eab49645e
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86702
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Renames ish_fw.bin to trulo_ish.bin to prevent potential conflicts with
other Nissa projects. This aligns with the naming used in the
chromeos-zephyr-ish package.
BUG=b:397821047
TEST=Flash trulo, disassemble SSDT, search for trulo_ish.bin
BRANCH=none
Change-Id: I855ecc87ddb7b69c2c2c8e4287bd9d6ec2e2e991
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Deku design has a non-sequential mapping between CPU Type-C ports
and EC Typec-C ports. This patch maps the CPU Type-C port to the
correct EC Type-C port for the Intel re-timer driver.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
deku-rev1 ~ # cbmem -c |grep "USB Type-C"
[INFO ] USB Type-C 0 mapped to EC port 0
[INFO ] USB Type-C 1 mapped to EC port 2
[INFO ] USB Type-C 2 mapped to EC port 1
[INFO ] USB Type-C 3 mapped to EC port 3
Change-Id: I80fa45a5f40d15c86087dca98bd0fb80a9121e50
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86705
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds the parameter which allows for custom port mapping
between CPU Type-C port and EC Type-C port to accommodate the
non-sequential mapping. Mainboard code must configure this parameter
if the CPU Type-C port to EC Type-C port mapping is not sequential.
BUG=b:399032094
TEST=build and verify TCSS port and EC port mapping
Change-Id: Id92f942e5c6b27342777b3e6fd12aff264ccec1b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Now that pch_hda_audio_link_hda_enable is hooked up in soc code, enable
it in devicetree to enable the HDA audio link.
Change-Id: I3f902d9b994cb0aac75cda69476500ec7c47b763
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86696
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:86109 it was reported that some options incorrectly don't depend
on EC_DASHARO_EC. Remove `depends on` from all options and instead put
everything behind an `if EC_DASHARO_EC` to ensure options don't cause
issues with boards not using Dasharo EC.
Change-Id: If6303bf7f155749bfcf9145fb93b018247350009
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86698
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was disabled while debugging S0ix issues during development.
Re-enable it now that S0ix is functional.
Change-Id: Ieab5229474ef93e96908b70e5986949b406fc0fa
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86693
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't map more than 16MiB in ROM2 decode window when the SPI ROM
size is bigger than 16MiB.
TEST: amd/birman+ still boots with bigger SPI flash sizes.
Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit binds the cep_enable, enable_fast_vmode and
fast_vmode_i_trip voltage regulator SoC settings to the CepEnable,
EnableFastVmode and IccLimit UPDs respectively.
BUG=b:357011633
TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly
Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
