This reverts commit 6b446b991b.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.
BUG=NA
TEST=Customer platform with Raptorlake-P
Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Several pads were not configured or configured incorrectly. FSP was
correcting them, but adjust the config in coreboot so this is not
necassary.
The config aligns with all other Star Labs boards.
Change-Id: Id41ea5d2f4f4321526d25b27411dad02fbde90b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87261
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure pads that aren't connected to anything to PAD_NC.
Also, remove comments for these pads.
Change-Id: Iaee9f3fc5639d5147f5bdf45fb5311a0121e2c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87260
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I944744f103aa2d1c347856a059d3dd6231b219c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This updates the Flashmap (FMAP) descriptor to allocate 18MB to
Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake
(PTL) Reference Validation Platform (RVP) coreboot is used with
several types of RVP boards, and this layout with a 14MB BIOS is
very convenient for debugging and creating coreboot for certain
use cases and testing purposes.
TEST=Build the ptlrvp variant (ES) and check if the flashmap of
the coreboot is updated correctly.
Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Intel processor number X7433RE.
Based on docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
This patch adds support for the Fintek f81966d SuperIO,
which is very similar to the fintek/f81866d.
Datasheet:
- Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P
BUG=NA
TEST=Customer platform with F81966D, verified with 'superiotool -de'
Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87198
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The hardware monitor provides access to its address space via the base
address stored in LDN 0x4 at index 0x60/0x61. There is no need to set
the configuration mode here, since the registers in the LDN are not
programmed.
Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The HWM port is +5 to the base address stored in LDN 0x4 at index
0x60/0x61. Take this rule into account when configuring the monitor,
as it was done for Fintek SIO chips in the superiotool utility [1].
[1] commit d92745b
TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which
is architecturally compatible) with pnp_write_hwm5_index() in the HWM
initialization code:
- the fans are regulated correctly;
- superiotool prints the values of the configuration registers updated
during initialization.
Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Harrie Paijmans <hpaijmans@eltan.com>
commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0")
caused a build failure for all mainboards that generate their FMAP
from the IFD (so intel only) instead of providing one themselves.
Jenkins didn't catch that, because apparently all mainboards that have
the IFD in the 3rdparty/blobs repository provide a custom FMAP.
So there was no defconfig that jenkins tested that would come across
this issue.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87288
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the AOAC IDs of the I3C controllers. The following documentation was
used to verify this:
Genoa: #55901 Rev 0.40
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
Change-Id: I54d049c58756251506f94d220e1970ccec170918
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87279
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add minimal common AMD I3C controller code that reports the MMIO region
used by the different I3C controllers to the resource allocator. For
this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig
option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C
device devicetree entries on all SoCs that include I3C controllers.
Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the base addresses of the I3C controllers and the mmio devices to
the devicetree for the SoCs that have I3C controllers. The following
documentation was used to verify this:
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
For Genoa, those entries already existed in both its iomap.h and its
devicetree. Cezanne and Picasso don't have I3C controllers.
Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST: Tested by entering ACPI S3 sleep state and pressing any key
on USB keyboard wakes up the system.
Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that the ROM2 MMIO area starts at flash address 0.
Document 56780
Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When a SPI ROM greater than 16MByte is being used it will be split
into 16MByte chunks that can be remapped in HW as an automatic recovery
mechanism. As an example when the EFS in the first 16MByte is corrupted
and the second 16MByte EFS is valid the HW will switch pages. The automatic
address translation of the MMIO ROM needs to be accounted when accessing
the ROM2/ROM3 BAR.
Add a function to retrieve the current address remapping and print it in
show_spi_speeds_and_modes() for debugging purposes.
Document 56780
Change-Id: I046e029e6135ab57f79b675c62b233203f00d705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to MediaTek's proprietary PI_IMG parser, two cookies (one
header and one footer) are expected. Therefore, add a script to perform
validity check of the PI_IMG firmware, so that format errors could be
caught in build time.
Change-Id: I27011492c7fab747aa3ee12d514d20a6a52d0a4d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87226
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After CB:86803, ${branch} variable is no longer valid. Use
${branch_name} instead ${branch} for generating the commit message.
TEST=./util/scripts/update_submodules -R 3rdparty/arm-trusted-firmware/
The script generates the new commit successfully.
Change-Id: Ia528379b8721e6d419984bab28de7cf427e42423
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87268
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Touchscreen function for Guren project.
Touchscreen panel: HKO RB116AS01-2,
and set TOUCHSCREEN_FTSC1000 to value "3".
BUG=b:391281767
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87238
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for
Panther Lake SoC has been removed.
Panther Lake platforms inherently enable display across all boot
modes (normal, developer, recovery) when vboot is active.
Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY`
becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY`
is enabled due to the selection of `BMP_LOGO` for ChromeOS
devices.
TEST=Able to perform ec sync without any additional reboots.
Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `display_init_required` function for vboot now mandates that either
`CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or
`CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled.
If neither of these Kconfig options is set when `CONFIG_VBOOT` is
enabled, the code will now trigger `dead_code()`. This enforces the
requirement that display initialization is explicitly requested or
always enabled when vboot is active, aligning with the intended usage
of `VB2_CONTEXT_DISPLAY_INIT`.
TEST=Able to build google/fatcat.
Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the initialization logic for the optional QUPv3 wrapper 2.
Add a runtime check of the `QUP_WRAP2_BASE` macro's value within
`qupv3_fw_init`.
This approach simplifies the QUP wrapper 2 initialization, making the
code flow depend directly on whether a valid base address is defined
for the target SoC.
To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as
a dummy entry) for SoCs like sc7180 and sc7280 which do not include
this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly
evaluate to false for these platforms, skipping the initialization.
Platforms that do have QUP wrapper 2 should define its non-zero base
address.
TEST=Able to build google/herobine.
Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a conditional bypass for ME state setting,
potentially reducing CBFS traversal time when searching for the
`option/me_state` file.
TEST=Able to build and boot google/fatcat.
Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the default heap size from 1MB to 2MB (0x200000) to
accommodate rendering high-quality firmware splash BMP logos.
The previous 1MB heap size might be insufficient for larger, more
detailed OEM logos, potentially leading to memory exhaustion during the
splash screen display.
TEST=Able to render an OEM logo size ~512KB w/o any corruption.
Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87265
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD SoC from family 17h share common cpu init code.
Move those to common/block/cpu/noncar/cpu.c
TEST=Build for glinda SoC & check for boot.
Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.
[1] commit da54bd60af ("Documentation: Update information about
intelp2m")
Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update SoundWire driver to support ALC712 audio codec.
reference datasheet: Realtek ALC712-VB-CG Rev. 0.24
BUG=b:378629979
TEST=emerge-fatcat coreboot
A sound can be heard from the speaker,
the test instructions are as follows:
amixer -c 0 cset name='rt712 OT23 L Switch' on
amixer -c 0 cset name=''rt712 OT23 R Switch' on
amixer -c 0 cset name='rt1320-1 OT23 L Switch' on
amixer -c 0 cset name='rt1320-1 OT23 R Switch' on
amixer -c 0 cset name='Speaker Switch' on
speaker-test -D hw:0,2 -c 2 -t sine -f 440
Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Previously only tested on server platforms - it wasn't working correctly
on consumer platforms due to missing boolean.
This patch fixes it, which makes resource allocator use uint64 instead
of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now
work correctly with ReBAR enabled, and correctly initialize the
framebuffer in payload (i.e EDK2) after initializing the OpROMs.
Example of issue caused by resource allocator using uint32 (Intel Arc
A580):
[ERROR] Resource didn't fit!!!
[ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned
[ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned
(Followed by Linux reporting that BAR space was limited to 256MB, which
severely hindered the performance).
TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD
Radeon RX7800XT.
Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad
is already configured as APIC interrupt, so simply define the
TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake.
TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not
complain on TPM interrupt not working. Check Windows Device
Manager does not report any problem with TPM and its resources.
Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87051
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log :
000000013fff0000-000000013fffffff: RESERVED
000000023fff0000-000000023fffffff: RESERVED
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This doesn't change any text - it just reformats the existing document.
- reflow paragraphs to 72 characters
- Put examples inside pre-formatted text blocks
- Adds spacing before section markers
Change-Id: I83925a4469e264da5887334e2584466cef089503
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Add USB host function support.
BUG=b:379008996
BRANCH=none
TEST=boot to kernel successfully from USB drive
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
