This commit introduces changes to the ACPI implementation for the
PTLRVP mainboard by adding power meter support. It defines how the
PAC194x series devices are connected to the I2C controller and details
their configuration. Each device under scope \_SB.PCI0.I2C3 is given
specific methods to indicate its status, resource settings, and device
specific configurations via _DSM. This includes functionality to return
monitored power rail names, resistor values, EMI configurations, sample
frequencies, and Vbus multiplication factors. These changes enhance
the power management capabilities of the mainboard, allowing precise
monitoring and control over various power rails.
BUG=none
TEST=Verify power meter ACPI changes in DSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6e5d38500cac46187283481ef6f84215b14e927b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
As a result of hardware BOM design, U51 (power gate for touchscreen)
would be required to remove on non-touch SKU. The change will cause
the I2C1 touchscreen devices probe ERROR of non-touch SKU since no
power for I2C bus pull-high resistors.The ERROR is waiting I2C stop
condition time out then bootperf test will get fail.
The CL apply fw_config field 19 - PANEL_PWR_SEQ_CTRL for I2C1:
0...disable (non-touch sku)
1...enable (touch sku)
Turn off I2C1 for non-touch sku, and keep I2C1 is on for touch sku.
It will avoid the touchscreen probing error on I2c1.
BUG=b:447513390
TEST=Check boot to kernel time is 1,376 sec under spec and without
I2C probe error in ap log of non-touch sku.
Check touchscreen device works well of touch sku.
Change-Id: I72a68177a90cea88fe283d8499b8378c64206fa2
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Update Kconfig.name with device/product names where available. Names
were parsed from a ChromeOS Recovery image config file, and matched
to the appropriate board using a script generated by Cursor AI.
Output was spot checked for correctness and compared to other sources.
Development devices were dropped from the results.
Change-Id: I5ac1c153606b7d1f93ea5c72e5ff727bb1f38683
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Update the DPTF parameters as provided by thermal team.
1. Adjust the PSV threshold value of the Passive Policy.
BUG=b:449890912
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: I8be7da7550994f6a408e2c5bbc6ae4d31fa22ada
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89564
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The hardware is mostly identical to the well supported Thinkpad T480
aside from some swapped PCIe clock lines. Consequently, coreboot will
boot to the OS in combination with a properly deguarded Intel ME.
The VBT was obtained from the latest stock BIOS (1.43, N27ET57W) with
intelvbttool. GPIO assignments have been cross-checked against publicly
available schematics (Tachi-2).
The patches have been validated on a Thinkpad T580 P/N 20L9-001NUS. With
SeaBIOS rel-1.17.0-4 as payload, the system boots into Linux (debian 13)
and Windows 10 22H2 with the hardware working as expected.
Change-Id: Iaa8368aeda11560bc0c1c77e7611ed9879d038da
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89499
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both of these boards have 20Gbps TBT2 ports, capable of accessing
PCIe labels from the PCH. Therefore, select
SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.
Change-Id: I4528f2748d1fa3988296f695dac045de536c43df
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The second port was set to 07.0, which is the first port. Correct
this.
Change-Id: I8d1a046ea863beb921c103cb2aa82b09d75f2be7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set pads that are not used to PAD_NC
Change-Id: I1a50bc8eab9d086b71cc33f56789bdd10f133864
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It seems that FSP was fixing up the TBT0 TXD and RXD GPIOs;
add the missing GPIO configuration and group them.
Change-Id: I22af542fe008395a47c64396f481442ff3bcc9a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89584
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Emply the standard Star Labs format for the config straps; this is
a non-functional change - just easier to read.
Change-Id: I04c7a8046c21577154593996866448fc4c05d03b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set pads that are not used to PAD_NC.
Change-Id: I3bf005b743fdcaf75c456c59354e7440ec0faefb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89581
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Apply the standard format for configuring the config straps. The
configuration of the straps isn't changed, just written more clearly.
Change-Id: I2cf130fbf7572a4014e97c14885951e5f604cfa8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Non-functional change that makes it easier to see what is actually
configured.
Change-Id: I2ffb11ef73a0b2c9e5236b2edb9ec187a045374c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RW_A and RW_B firmware sections are increased by 256KB, from 1500K
to 1756K, to support larger firmware images. With bootsplash enabled,
the remaining space in these sections is approximately 15KB, which is
insufficient to hold the bootsplash assets. This increase provides the
necessary space. Additionally, with more features anticipated from the
payload (depthcharge), this extra space serves as a reserve to prevent
future build failures due to insufficient space.
The RW_LEGACY section is also adjusted to fill the remaining space.
WARNING: Please do NOT cherry-pick to rauru firmware branch.
BUG=b:450510630,b:319511268
TEST=emerge-rauru coreboot chromeos-bootimage (with BMP_LOGO enabled)
Change-Id: I70aaa9e7011b7f2376b7bc28caac27c0a86aa20a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Commit 743e3a07f5 ("mb/google/brya/var/nissa: Remove duplicate ACPI
device GFX0") removed the GMA default panel and replaced it with the
generic gfx device, but left out the device type field, which resulted
in changes to the _DOD and _ADR methods for the GFX0 ACPI device.
This change caused Windows to ignore the ACPI brightness controls,
leaving the display fixed at full brightness. Add the missing device
type entry to restore the brightness control functionality.
before (incorrect):
_DOD: 0x80010000
_ADR: Zero
after (correct):
_DOD: 0x80010400
_ADR: 0x00000400
TEST=build/boot Win11, Linux on craaskvin, verify brightness controls
functional under both OSes.
Change-Id: Ia0cfcec14963605ce874c6c7ed6b26c725cf74f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
SATA_DEVSLP1B and PEDET were simply missed, so configure them
Change-Id: Iface1f19c5a93f5a911861fbad7fa4b3f808bfef
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, it just puts them into a the same
format as the other Star Labs boards.
Change-Id: I849d0b50490eec6b6c58bd0fd29f57e434ba95c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89575
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When Thunderbolt was disabled in the option table, only
VtdBaseAddress[3] was zero'd, when it should be
VtdBaseAddress[4] as well.
Change-Id: I63e3cefcb74c2ef31b5b0180d13a4720a6d7d0c2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89553
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, as the settings remain the same, and
it's only done as a pre-caution as FSP has been funny with VBT versions
before.
Change-Id: Ie7978e76286b3e2ff21fd0a28bfe51bdfd32f381
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89547
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add BT _PRR related methods to mitigate BT lost issue.
Refer to Intel TA#837249, toggling BTEN, BT_IF_SELECT, and
BT_RESET_GPIO to recovery BT device when BT became a low-speed usb
device.
BUG=b:451095940
TEST=Run reboot stress and check kernel log, BT could be recovery.
usb 3-10: new full-speed USB device number 4 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
usb 3-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0
usb 3-10: using ACPI '\_SB.PCI0.XHCI.RHUB.HS10' for 'reset' GPIO lookup
usb 3-10: USB disconnect, device number 4
usb 3-10: new low-speed USB device number 5 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new low-speed USB device number 6 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new full-speed USB device number 7 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
Change-Id: I0d485a9102676624da28d5d681ea4510444e17bd
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89384
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
ReportingPchPmDisableEnergyReport has been 0 by default in all
FSP versions up until Meteor Lake. Set this to unify the
configuration between boards.
No applicable tests.
Change-Id: If9cdbb466bf8e4efc7a1577b0a1fec6270550d05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89527
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These do not need to be configured, as they're configured
automatically on reset.
Change-Id: I26c9a42fa44b55208583859895f9a39016e76eac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89523
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When configuring the touch_thc_i2c controlled touchpad and touchscreen
for the first time, referring to the fatcat code. The touchpad and
touchscreen could not be successfully bringup, since the touchpad and
touchscreen configured in the code are opposite to those in the fatcat
schematic diagram. According to the circuit schematic
NB7835CAA_SCH_MB_V1_A.pdf, modify the GPIO configuration and devicetree.
1. Configure GPIO as THC-I2C function.
2. Modify devicetree
touchpad ==> THC0
touchpanel ==> THC1
BUG=b:448030832 b:445817408
TEST=emerge-fatcat coerboot chromeos-bootimage
flash to DUT, touchpad and touchpanel can be found by `getevent`
Change-Id: I6826145f58d437e03683a4459ded3b7657cf616a
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89383
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the PinMux is configured correctly, these no longer
need to be set, as they're configured automatically on reset.
Change-Id: I03c6431f6ce7118444ef3672de32c5afa2e36441
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This doesn't do anything, so remove it.
Change-Id: Ic753d0f08bdc0e9dd839357eb73c9771d94e5c83
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure Pin Mix for Cs, Clk, Miso and Mosi to get the eSPI
GPIOs working as they should be.
Change-Id: I798f1e98f611a53e9c87f15e1e0f1679b9933bee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89520
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common settings are:
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFPx that are not present.
* eDP panel colour depth is 24-bit (8 bpc).
* POST brightness of 100.
* Minimum brightness of 0.
* DPST level of 2.
* PSR Enabled.
* DDRS Enabled.
Test=Boot all boards, check brightness levels are consistant, the
kernel recognises that PSR and DDRS are enabled, check all outputs
work.
Change-Id: I7eb6a110d25d4bcfd26ffdddd9ec666fc90a04b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89515
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macro USB2_PORTS_MID vs USB2_PORTS_TYPE_C essentially enables
or disables the PortResetMessage. This is only relevant to TCSS
ports.
Correct the macros accordingly.
Change-Id: I18a078c7f6fb937293e6159f05587b7e1f881512
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89513
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't supported so remove it.
Change-Id: I8e8a87f1394199d3288ae27601069ad88e2fa74f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...
According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.
BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.
Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Elan touchpad configuration for moonstone AVL.
BUG=b:442964901
TEST=build firwmare and check the touchpad can work well in ALOS.
cat /sys/bus/i2c/devices/i2c-12/i2c-ELAN0000\:00/name
i2cdetect -y -r 12 -> 0x15 = UU
Change-Id: Ie105906fb54383dbf91513f81ab933653162ad4e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89467
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:442964901
TEST=emerge-fatcat coreboot and focaltech touchscreen can work well.
Change-Id: I7fb2f8b3c4ceb9d4bc7471d7eef23b0a18dca78a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89465
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard family is set based on the baseboard.
TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.
Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.
TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.
Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.
BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot
Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Options are organized to be as close to vendor firmware as possible.
Some options are not implemented for all variants. Those are either
excluded from build via preprocessor, or left visible but unused.
They will be squared off later.
TEST=abuild tested on the whole series.
TEST=Complete platform setup menu appears for mb/asus/p8z77-v_le_plus
with edk2/mrchromebox payload, with changes to front audio panel type
reflected in hardware.
Change-Id: I558012b28d098a90863e3ff6610017c2410c23ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
