The ctags tool (called by ctags-project target) currently complains
about not finding certain files:
```
ctags: Warning: cannot open input file "bl31/aarch64/bl31_entrypoint.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/aarch64/crash_reporting.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/aarch64/runtime_exceptions.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31.ld.S" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_context_mgmt.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_main.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/bl31_traps.c" : No such file or directory
ctags: Warning: cannot open input file "bl31/interrupt_mgmt.c" : No such file or directory
ctags: Warning: cannot open input file "common/aarch64/debug.S" : No such file or directory
ctags: Warning: cannot open input file "common/bl_common.c" : No such file or directory
ctags: Warning: cannot open input file "common/fdt_fixup.c" : No such file or directory
...
```
The project_filelist.txt generation includes the compiler
generated "*.d" files, except for files found in build/util. Most file
paths in these "*.d" files are file paths relative to the root
directory of coreboot. Some projects though are compiled separately from
coreboot (e.g. payload, vboot, util). Some of these (e.g. util, vboot)
are also put into the build directory of coreboot and relative file
paths are relative to these projects instead of coreboot. This has the
uncanning side effect that the ctags Makefile target can't find these
files, since they are not relative to the coreboot root directory.
This patch excludes the build/3rdparty directory from those files, since
they contain 'separately' compiled projects like
3rdparty/arm-trusted-firmware.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I18d0377e327530d9ef9382c324a305d156c5c681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86868
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is just simply incorrect, as these signals are used to
pull various devices into low power states during S3.
Change-Id: Ic2950cc43fd17dda4205964c851b09cfd86d90d9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set PsysPmax to 0, which is auto instead of the FSP default
which is 21.5W (0xac).
Change-Id: Ia2503077067fa719a09f9877d7fe0bedf2a662f1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This adds the release notes template for the upcoming June release of
coreboot.
Change-Id: Ia8aa266973181be12620343eb58bb9ba8f0ccc79
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87030
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select UFS or eMMC as the active storage of meliks boards by using
`STORAGE` field in `FW_CONFIG`.
BUG=none
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot
Change-Id: Ifcc917ad1231fa68ce4caf6f0d67fa75b16a3085
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86980
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI S3 suspend has been failing on this mainboard for about 5 months
as of this writing. This move fixes the regression. The removal of
these three settings from devicetree also realized a small image
size reduction.
TEST=Now again able to enter S3 suspend and return to where I was.
Change-Id: I35189b7977c83b3a2666dded8267b9021f0ea3f3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
By doing this the base port is now #defined as CONFIG_SUPERIO_PNP_BASE,
available to both C and ASL code, the latter will soon start to make
use of this as well. This will be gradually expanded to all boards using
superio/nuvoton/{nct5572d,nct6776,nct6779d,nct6791d}.
Change early_init.c of all variants to use this new #define.
Change-Id: I6e2851db68f4867be8fa4ef0d8bd8d1b9b8bf92a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86635
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on a mix of existing P8x7x series boards, boardview, vendor
firmware dumps, and hardware testing.
Working:
- SeaBIOS 1.16.3 and edk2/mrchromebox/uefipayload_2501
- Serial port
- All USB2 & USB3 ports
- Z77 SATA ports
- Integrated graphics thru all ports with libgfxinit
- RTL8111F LAN (MAC address doesn't stick)
- Analog 7.1 audio out the back panel jacks
- Digital audio
- Front HDA audio panel
- PCIe x16 slot with nVidia 8800GT GPU
- PCIe x1 slots
- PCIe x4 slot with Intel Octane H10 1TB NVMe
- PCI slots
- Hardware monitoring and fan control
- S3 suspend
Untested:
- Hotplugging Z77 SATA ports
- EHCI debug
Not working:
- PS/2 mouse
- Wake on LAN
- Marvell SATA ports
Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86172
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extends commit 57946ad817 ("mb/asus/p8z77-m[_pro]: Blink power
LED during suspend") to the entire family.
Also, we don't need the 0x for Arg0; it can't go larger than 5.
Applied this patch and CB:82556 while developing a port for
P8Z77-V LE PLUS variant (which uses GPIO8 for power LED). Its
power LED does blink during suspend.
Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All boards in the family have the negative leg of power LED linked
to a PCH GPIO pin, either GPIO 27 or 8.
After examining their boardviews, mark p8h77-v and p8z77-v_lx2
variants through Kconfig as using GPIO8 for power LED.
Change-Id: I4d42cd9ac497a4200ab5c90d09eb4dbab8917b30
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the PCI device is already enabled, include the ACPI stub so the
OS driver can attach.
TEST=build/boot Win10 on google/volteer (drobit)
Change-Id: I9f9edcdd3c32d66af64878b6d8735019bccddd26
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000
APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.
This time increase the size properly by adjusting the base address of
the components that come after the APOB region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I070cf766b98825cd5ff37674e1f9651fa71159c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reverts commit 362232d236.
Reason for revert:
This introduced an overlap between APOB DRAM region and SHAREDMEM
region used for PSP verstage. Our linker scripts would have caught that,
but we don't have any glinda based mainboards using VBOOT in the tree
at the moment so there is no actual overlap on any upstream mainboards
at the moment. Still if VBOOT based mainboards are added in the future
it would cause a build error for them.
The next patch in the train will increase the APOB NV size properly by
increasing all the other addresses in the chain too.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4b4cb4104a59f72491a941dc1d13018f2389bb03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86861
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the Port Reset Message for the two USB Type-C ports.
Change-Id: I181db4cfd3a50915337816c91f1b2feb3f874b06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87018
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the PRRS object that is used in the _RST method.
Change-Id: I935fae3c215e48288d8856d7be5cacc4e261d86f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87005
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This pad is connected, so configure it accordingly.
Change-Id: I3ef2fd3793c31a6e2f62ff621ab0ed9bb4595b79
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87014
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pin is connected, so configure it to NF2 accordingly.
Change-Id: Iae8730a875fa0b2f4036f278591ece5a5fa5c5d1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87012
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than setting the pads to Not Connected for low, configure
them as output GPIOs driven low; this isn't a functional change,
but just makes it easier to read.
Change-Id: Ia8fa495ff9a7b25195fbf39b4090bc57a48bf4e8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is conected to the Top Swap Override strap, so add comments
to that effect, and an explicit config to disable it.
Change-Id: I183fc60c61ec82f0d27a0d3726f0d3c37ddee04a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87010
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO isn't conencted, so configure it accordingly.
Change-Id: I2b027a1181de67e9a33bbb2062573c071827134a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Meteor Lake doesn't seem to configure the eSPI GPIOs for S3 on
reset, so add configuration from them so coreboot can configure
them correctly.
Change-Id: I4b74d320977faa60441e3d8b12980ef6ec41549d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87008
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comment was reversed for the eSPI strap, so the GPIO was
misconfigured. Correct the comment and config accordingly.
Change-Id: I494d247ea4625fa1633ffa6d073b48f1dbf8432f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
config->cnvi_wifi_core and config->cnvi_bt_core are false by
default. This commit suppresses the acpi/acpigen.h inclusion, which is
unnecessary as well.
Change-Id: I2e171d6388b472f4cb877fdd93771142f9a3f2de
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Other types of FWs in the BIOS table are defined by context. So the
BIOS binary should follow that.
TEST=Binary identical test on platforms before mendocino
Tested on Skyrim
Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85466
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Process the single SPD data file which resides in cbfs. Add Kconfig
switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex
into the build by adding a correspondig Makefile.mk in the spd folder.
Additionally to load the memory configuration FSP-M parameters for the
romstage are set.
Loading SPD data from HWILIB was the technique applied by mainboard
siemens/mc_ehl2 from which this mainboard was copied. On fa_ehl
SPD data is stored in CBFS and gets loaded from there.
Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
It is more reasonable. And, in later change, the Level 1 should be
split with Level 2 and combined with EFS.
Change locate_bdt2_bios to locate_bdt_bios. This function is more
flexibile and covers both L1 and L2 BIOS directory table.
Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84532
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now drawn (indirectly) from main usb_port_config.
Also drop it from autoport.
Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As of commit a3d1e6c480 ("sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping"), this is now linked to main USB port config
and is no longer referenced separately.
This board is the last unresolved mismatching xhci_overcurrent_mapping
and there is no reports whether it is working or broken. Since the
value is no longer used anyway, remove it and put a FIXME in its place.
Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This board has an effectively broken USB configuration, which made
itself known during testing on a Pro 6300 SFF, that could run an
unmodified build for this variant and actually share the same vendor
BIOS update file (sp95971 v3.08 rev A).
Further examination of the BIOS update reveals five possible sets
of USB port configurations for all models covered by that update,
selected by PCH GPIOs 38 & 49, none of which matches what was currently
coded.
Then I received the autoport log from hardware with vendor BIOS that
confirmed my theory. Therefore apply the USB port config found therein.
While I'm at it, remove xhci_overcurrent_mapping, made obsolete by
commit a3d1e6c480 (sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping).
Change-Id: Idc469b1aedcad2978247b9f6efbc7f55964e9ed1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.
This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.
Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.
BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.
Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FW_CONFIG_SOURCE_CBFS option serves as a backup for
FW_CONFIG_SOURCE_CHROMEEC_CBI, utilizing variables stored in CBFS.
When using ChromeEC CBI as the firmware configuration source,
changes to fw_config values can be made without updating the firmware
image. However, using CBFS as the configuration source requires
resigning the firmware because the current implementation reads from
the RW firmware region (FW_MAIN_A/B), necessitating resigning for
updates. To avoid this step, the code should be modified to use the
RO CBFS for fw_config values instead of the RW (Read-Write) CBFS.
TEST:
1. Add FW_CONFIG_SOURCE_CBFS in board Kconfig and build image
2. Modify fw_config value by cbfstool with built image
3. flash and boot up system
4. Check updated fw_config value
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4710a1043fe75888d2dcaee98c6957e6bd639be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86943
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Update device tree to support Focal touchpad.
BUG=b:404363997
TEST=emerge-fatcat coreboot and Focal touchpad can work well.
Change-Id: I515eb63a9e5b8e4ebc7d6828ae3da47caa997ea3
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86979
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply the change made to brya/redrix in CB:86749 to all applicable brox
variants, which is currently jubilant only.
BUG=b:397355818
TEST=Dump SSDT on jubilant
Change-Id: Ie0fc00e511b8efd5bae29cc089a24f7b0128d77e
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86954
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pad isn't used, so set it to not connected.
Change-Id: Ic7174457f56e64751718dc10227ec07b793559eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86988
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit configures the GPIO_SLP_S0_GATE pin for the francka and
felino mainboards, which are used to gate the SoC's SLP_S0# signal
for proper sleep state management.
- For francka, GPIO_SLP_S0_GATE is set to GPP_F23.
- For felino, GPIO_SLP_S0_GATE is set to GPP_D03.
The base fatcat board and its variants (fatcatnuvo, fatcatite,
fatcatish) do not utilize this pin, therefore it is defined as 0
(Not Connected).
Change-Id: I3150d4e60e4886fb7df7229eaf9efed59a69a707
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86984
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
The fatcat variant now handles SLP_S0 pin functionality natively,
removing the need for HAVE_SLP_S0_GATE. However, other variants like
felino and francka boards still rely on this Kconfig option for proper
sleep state gating. This commit re-enables it for these specific boards.
TEST=Able to build and boot google/fatcat.
Change-Id: Ib7e683c3fee575245e8796638260f1fd8e6e5c34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86983
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables EC software sync specifically for the Microchip EC
on the fatcat/fatcat-ish board. This change selects
`GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC` for boards w/ microchip EC
(EC_GOOGLE_CHROMEEC_MEC) like fatcat and fatcat-ish.
This allows other fatcat variants (Nuvoton, ITE EC AIC) to potentially
enable EC software sync, which is not compatible with the Microchip EC.
BUG=b:368278795
TEST=Verified EC software sync functionality on a Nuvoton AIC fatcat
variant.
Change-Id: I33c82c05a810c0328de5513f452505f2d560cf91
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86982
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.
Change-Id: Iefe8abc9741f9a77b7d55168a0ac42bf607fdb7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
to which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map the
"permanent" regions below 4GiB, these temporary regions below 4GiB, and
any RAM above 4GiB due to fragmentation in the various ranges, as well
as limitations on the area covered by a single MTRR due to how they
are stored in the CPU registers.
As a workaround, if the number of MTRRs needed for the temporary map
exceeds the maximum available for the system, retry calc_var-mtrrs()
with `above4gb` set to false.
TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.
Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Cleans up a nit identified by Martin when adding a very similar
variant.
Change-Id: Id19054c08643cf03b2afbfe4c8929ce9dacaea5c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Since CNVI BT Offload is not yet ready on Pantherlake and HW already
soldered these 4 pads connection onto the board, therefore keep
Pad Config NC_LOCK and BT offload disable.
BUG=b:397578690
Test=emerge-fatcat coreboot and make sure WIFI/BT works
Change-Id: I2d84e8cff499d462133143b12fa6335e76323926
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86944
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This reverts commit 2da8d8affc.
Reason: The ISH firmware is renamed to trulo_ish.bin in the rootfs
itself hence this change is not required.
BUG=b:401138236
TEST=S0ix on Trulo and Truloti.
Change-Id: Ic21c9e2a28113dbd58ac992a380df601d058b16c
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86976
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables the crossystem utility to access WP GPIO.
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: Iedf4d73a85e4159b4236e13d6aa8ff5e6fe2fcb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
