mb/siemens/fa_ehl: Configure LPDDR4 from CBFS

Process the single SPD data file which resides in cbfs. Add Kconfig
switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex
into the build by adding a correspondig Makefile.mk in the spd folder.
Additionally to load the memory configuration FSP-M parameters for the
romstage are set.
Loading SPD data from HWILIB was the technique applied by mainboard
siemens/mc_ehl2 from which this mainboard was copied. On fa_ehl
SPD data is stored in CBFS and gets loaded from there.

Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Johannes Hahn 2025-02-13 10:14:12 +01:00 committed by Matt DeVillier
commit 50178229ff
8 changed files with 26 additions and 24 deletions

View file

@ -6,8 +6,9 @@ config BOARD_SIEMENS_BASEBOARD_FA_EHL
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select HAVE_ACPI_TABLES
select USE_SIEMENS_HWILIB
select HAVE_SPD_IN_CBFS
select SOC_INTEL_DISABLE_POWER_LIMITS
select USE_SIEMENS_HWILIB
config BOARD_SIEMENS_FA_EHL
select BOARD_SIEMENS_BASEBOARD_FA_EHL

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@ -1,5 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
subdirs-y += spd
bootblock-y += bootblock.c
romstage-y += romstage_fsp_params.c

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@ -1,10 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/dram/common.h>
#include <device/mmio.h>
#include <hwilib.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <string.h>
@ -14,23 +12,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
{
static struct spd_info spd_info;
const struct mb_cfg *board_cfg = variant_memcfg_config();
static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE];
const char *cbfs_hwi_name = "hwinfo.hex";
/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
memset(spd_data, 0, sizeof(spd_data));
if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
(hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
(ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
spd_info.read_type = READ_SPD_MEMPTR;
} else {
die("SPD in HW-Info not valid!\n");
}
/* Initialize variant specific configurations */
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false);
bool half_populated = false;
spd_info.read_type = READ_SPD_CBFS;
spd_info.spd_spec.spd_index = 0x00;
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
/* Enable Row-Hammer prevention */
memupd->FspmConfig.RhPrevention = 1;

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@ -0,0 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = Nanya_NT6AP512T32BV-J1I # 0b000

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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#include <stdint.h>
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
#endif

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@ -4,7 +4,3 @@ bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += mainboard.c
SPD_SOURCES = Micron_MT53E512M32D1NP-046WTB.spd.hex
LIB_SPD_CBFS := $(foreach f, $(SPD_SOURCES), \
src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>