mb/siemens/fa_ehl: Configure LPDDR4 from CBFS
Process the single SPD data file which resides in cbfs. Add Kconfig switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex into the build by adding a correspondig Makefile.mk in the spd folder. Additionally to load the memory configuration FSP-M parameters for the romstage are set. Loading SPD data from HWILIB was the technique applied by mainboard siemens/mc_ehl2 from which this mainboard was copied. On fa_ehl SPD data is stored in CBFS and gets loaded from there. Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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8 changed files with 26 additions and 24 deletions
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@ -6,8 +6,9 @@ config BOARD_SIEMENS_BASEBOARD_FA_EHL
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select HAVE_ACPI_TABLES
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select USE_SIEMENS_HWILIB
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select HAVE_SPD_IN_CBFS
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select SOC_INTEL_DISABLE_POWER_LIMITS
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select USE_SIEMENS_HWILIB
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config BOARD_SIEMENS_FA_EHL
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select BOARD_SIEMENS_BASEBOARD_FA_EHL
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@ -1,5 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-only
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subdirs-y += spd
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bootblock-y += bootblock.c
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romstage-y += romstage_fsp_params.c
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@ -1,10 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <device/dram/common.h>
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#include <device/mmio.h>
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#include <hwilib.h>
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#include <soc/meminit.h>
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#include <soc/romstage.h>
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#include <string.h>
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@ -14,23 +12,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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static struct spd_info spd_info;
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const struct mb_cfg *board_cfg = variant_memcfg_config();
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static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE];
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const char *cbfs_hwi_name = "hwinfo.hex";
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/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
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spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
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memset(spd_data, 0, sizeof(spd_data));
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if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
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(hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
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(ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
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spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
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spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
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spd_info.read_type = READ_SPD_MEMPTR;
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} else {
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die("SPD in HW-Info not valid!\n");
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}
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/* Initialize variant specific configurations */
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memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false);
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bool half_populated = false;
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spd_info.read_type = READ_SPD_CBFS;
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spd_info.spd_spec.spd_index = 0x00;
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memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
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/* Enable Row-Hammer prevention */
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memupd->FspmConfig.RhPrevention = 1;
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3
src/mainboard/siemens/fa_ehl/spd/Makefile.mk
Normal file
3
src/mainboard/siemens/fa_ehl/spd/Makefile.mk
Normal file
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@ -0,0 +1,3 @@
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## SPDX-License-Identifier: GPL-2.0-only
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SPD_SOURCES = Nanya_NT6AP512T32BV-J1I # 0b000
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14
src/mainboard/siemens/fa_ehl/spd/spd.h
Normal file
14
src/mainboard/siemens/fa_ehl/spd/spd.h
Normal file
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#include <stdint.h>
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void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
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void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
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void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
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void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
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#endif
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@ -4,7 +4,3 @@ bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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ramstage-y += mainboard.c
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SPD_SOURCES = Micron_MT53E512M32D1NP-046WTB.spd.hex
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LIB_SPD_CBFS := $(foreach f, $(SPD_SOURCES), \
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src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
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@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/meminit.h>
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#include <soc/romstage.h>
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