mb/google/fatcat: Configure GPIO_SLP_S0_GATE for francka and felino

This commit configures the GPIO_SLP_S0_GATE pin for the francka and
felino mainboards, which are used to gate the SoC's SLP_S0# signal
for proper sleep state management.

- For francka, GPIO_SLP_S0_GATE is set to GPP_F23.
- For felino, GPIO_SLP_S0_GATE is set to GPP_D03.

The base fatcat board and its variants (fatcatnuvo, fatcatite,
fatcatish) do not utilize this pin, therefore it is defined as 0
(Not Connected).

Change-Id: I3150d4e60e4886fb7df7229eaf9efed59a69a707
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86984
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>

src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h

@@ -15,15 +15,21 @@
 #if CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATITE)
  #define EC_SYNC_IRQ	GPP_E07_IRQ
  #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 #elif CONFIG(BOARD_GOOGLE_FATCAT) || CONFIG(BOARD_GOOGLE_FATCATISH)
  #define EC_SYNC_IRQ	0 /* Not Connected */
  #define GPIO_PCH_WP	GPP_D02
+#define GPIO_SLP_S0_GATE	0 /* Not Connected */
 #elif CONFIG(BOARD_GOOGLE_FRANCKA)
  #define EC_SYNC_IRQ	GPP_B05_IRQ
  #define GPIO_PCH_WP	GPP_E22
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_F23
 #elif CONFIG(BOARD_GOOGLE_FELINO)
  #define EC_SYNC_IRQ	0 /* TODO */
  #define GPIO_PCH_WP	0 /* TODO */
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_D03
 #endif
 
 #endif /* __BASEBOARD_GPIO_H__ */