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mb/asus/p8x7x-series: Move Super I/O base port to Kconfig

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By doing this the base port is now #defined as CONFIG_SUPERIO_PNP_BASE,
available to both C and ASL code, the latter will soon start to make
use of this as well. This will be gradually expanded to all boards using
superio/nuvoton/{nct5572d,nct6776,nct6779d,nct6791d}.

Change early_init.c of all variants to use this new #define.

Change-Id: I6e2851db68f4867be8fa4ef0d8bd8d1b9b8bf92a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86635
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2024-06-16 22:55:29 -04:00 • committed by Martin L Roth
commit e7f4a2c0d6
7 changed files with 19 additions and 15 deletions
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4
src/mainboard/asus/p8x7x-series/Kconfig
View file

@ -104,4 +104,8 @@ config CMOS_DEFAULT_FILE
config CMOS_LAYOUT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
config SUPERIO_PNP_BASE
hex
default 0x2e
endif

6
src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

4
src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
View file

@ -10,8 +10,8 @@
#include <option.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define GPIO0_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
void bootblock_mainboard_early_init(void)
{

2
src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
View file

@ -11,7 +11,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP2)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{