mb/asus/p8x7x-series: Add P8Z77-V LE PLUS variant
Based on a mix of existing P8x7x series boards, boardview, vendor firmware dumps, and hardware testing. Working: - SeaBIOS 1.16.3 and edk2/mrchromebox/uefipayload_2501 - Serial port - All USB2 & USB3 ports - Z77 SATA ports - Integrated graphics thru all ports with libgfxinit - RTL8111F LAN (MAC address doesn't stick) - Analog 7.1 audio out the back panel jacks - Digital audio - Front HDA audio panel - PCIe x16 slot with nVidia 8800GT GPU - PCIe x1 slots - PCIe x4 slot with Intel Octane H10 1TB NVMe - PCI slots - Hardware monitoring and fan control - S3 suspend Untested: - Hotplugging Z77 SATA ports - EHCI debug Not working: - PS/2 mouse - Wake on LAN - Marvell SATA ports Change-Id: Id9eef8b3426daecce0c95f56bfcd4caae2d52e50 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86172 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Documentation/mainboard/asus/p8z77-v_le_plus.md
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Documentation/mainboard/asus/p8z77-v_le_plus.md
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# ASUS P8Z77-V LE PLUS
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This page describes how to run coreboot on the [ASUS P8Z77-V LE PLUS].
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## Flashing coreboot
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```{eval-rst}
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Socketed flash | yes |
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+---------------------+----------------+
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| Model | W25Q64FVA1Q |
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+---------------------+----------------+
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| Size | 8 MiB |
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+---------------------+----------------+
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| Package | DIP-8 |
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+---------------------+----------------+
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| Write protection | yes |
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+---------------------+----------------+
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| Dual BIOS feature | no |
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+---------------------+----------------+
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| Internal flashing | yes |
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+---------------------+----------------+
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```
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### How to flash
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The main SPI flash cannot be written because the vendor firmware disables BIOSWE
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and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
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programmer is required. You must flash standalone, flashing in-circuit doesn't
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work. The flash chip is socketed, so it's easy to remove and reflash.
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See page 2-2 of user's manual for flash chip location.
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### Extra preparations for changing PCIe slot configuration
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On vendor firmware, the black PCIEX16_3 slot can be configured as x2 or x4.
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If set for x4, PCIEX1_1 and PCIEX1_2 are disabled.
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Before flashing coreboot for the first time, decide how you want to use the PCIe slots.
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If you want to be able to choose between using the two PCIEX1 slots and the PCIEX16_3 slot at
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x4 bandwidth, you need to do some preparation, namely make two backups of the whole flash
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chip, specifically the flash descriptor under both configurations.
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Enter vendor UEFI setup and check the PCIEX16_3 (black) slot bandwidth setting. You'll back up
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under this setting first. Once one backup is made, come back and change the setting
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from x2 to x4 (or vice versa) and reboot once, then make the other backup.
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With PCIEX16_3 (black) slot bandwidth at x2, run these commands:
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```bash
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flashrom -p internal -r pciex163_x2.bin
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dd if=pciex163_x2.bin of=ifd-pciex163_x2.bin bs=4096 count=1
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```
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With PCIEX16_3 (black) slot bandwidth at x4, run these commands:
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```bash
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flashrom -p internal -r pciex163_x4.bin
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dd if=pciex163_x4.bin of=ifd-pciex163_x4.bin bs=4096 count=1
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```
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(`dd` needs not be run as root.)
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Save the shortened `ifd-pciex163_*.bin` files for when you want to change the configuration.
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Keep one of the full backups as well.
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See "PCIe config" section below for more details.
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## Working
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- Core i5-3570K and i7-3770K CPUs
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- Corsair CMZ16GX3M2A1600C10 2x8GB memory kit
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- SeaBIOS 1.16.3
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- edk2 mrchromebox fork uefipayload_2501
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- Kernel 6.12.7
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- All USB2 ports (mouse, keyboard)
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- All USB3 ports
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- Z77 SATA ports (WD Blue SA510, Liteon LH-20A1L)
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- nVidia 8800GT GPU in PCIEX16_1 slot running x16
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- PCI slots (Sound Blaster Live! Value)
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- RTL8111F LAN
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- CPU temperature sensors and hardware monitor
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(see [below](#hardware-monitoring-and-fan-speed-control))
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- Integrated graphics with libgfxinit and VBT
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(all ports tested and working)
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- Both PCIe x1 slots when properly configured
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(see [How to flash](#how-to-flash) above and [PCIe config](#pcie-config);
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Atheros 928x miniPCIe Wifi on adapter & MSI Herald-BE Wifi7 adapter)
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- PCIe x4 slot with Intel Octane H10 1TB NVMe at x2 mode
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- Serial port
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- PS/2 keyboard
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- Analog 7.1 audio out the 3.5mm jacks on rear panel
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- Front HDA audio panel
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- Digital audio out (Optical, internal SPDIF header, HDMI, DisplayPort)
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Although a `spdif_dest` option is provided for feature parity with vendor firmware,
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it doesn't seem to matter and digital audio out is available through all ports.
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It does, however, change how the ports are presented to the OS.
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- S3 suspend from Linux
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## Known issues
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- RTL8111F here has no EEPROM for vital product data such as MAC address, which is also not
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being properly programmed. You may need to fuse your MAC address with [rtnicpg] instead.
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- For 7.1 analog audio to work, at least the front channel (green jack) must be connected.
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## Untested
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- Hotplug of Z77 SATA ports
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- EHCI debugging
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## Not working
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- Wake-on-LAN
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- PS/2 mouse (requires a patch currently under review)
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- Asmedia USB 3.0 battery charging support (for USB 3 ports on the LAN stack)
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- USB Charger+ (When the bottom USB 3 port on the eSATA stack, also used for BIOS flashback,
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remains powered while the rest of the system is off. Both features are controlled by the same
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AI1314 controller.)
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- Marvell SATA ports are brought up in IDE mode, pata_marvell driver is loaded,
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but are effectively unusable.
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## PCIe config
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See [Extra preparations](#extra-preparations-for-changing-pcie-slot-configuration) section above.
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Changing the PCIe slot configuration requires manipulating a PCH GPIO line and a soft strap in
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the flash chip's descriptor section, which is read-only at runtime. coreboot programs the GPIO
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to match the soft strap, but how it can update the soft strap itself is to be determined. Until
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then, to make this change you have to re-flash the descriptor yourself, with one of the two
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copies you previously saved per above:
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```bash
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flashrom -p internal --ifd -i fd -w ifd-pciex163_x2.bin
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```
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## Hardware monitoring and fan speed control
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Although all fan ports are 4-pin for PWM fans, only CPU_FAN has actual PWM control;
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all other fan speed control is by voltage only.
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Write 1 into `/sys/class/hwmon/hwmon1/pwm1_mode` to enable CHA_FAN1 control, otherwise it
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runs at full speed.
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`fan5`/`pwm5` is not implemented and should be ignored.
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These are the sensors.conf settings for this board:
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```
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label fan1 "CHA_FAN1"
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label fan2 "CPU_FAN"
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label fan3 "CHA_FAN2"
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label fan4 "CHA_FAN3"
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ignore fan5
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label in1 "+12V"
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label in4 "+5V"
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compute in1 @*12, @/12
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compute in4 @*5, @/5
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set temp1_type 4
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set temp2_type 4
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```
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## Extra onboard switches and LEDs
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- `BIOS_FLBK`:
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Vendor firmware uses this button to facilitate a simple update mechanism
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via a USB drive plugged into the bottom USB port of the USB/ESATA6G stack.
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It connects to the proprietary AI1314 controller, along with `FLBK_LED`.
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- `MemOK!`:
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OEM firmware uses this button for memory tuning related to overclocking.
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It connects to pin 74 of super I/O.
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- `DRAM_LED` lights up when there is a memory problem or when vendor MemOK! feature is
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operating. Connects to GP07 line of super I/O. coreboot lights it up during memory init
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similar to vendor firmware.
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- `EPU`: When enabled, lights up `EPU_LED` and takes PCH GPIO44 low.
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- `TPU`: When enabled, lights up `TPU_LED` and takes PCH GPIO45 low.
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`EPU` and `TPU` are cues to vendor firmware to enable two embedded controllers for
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overclocking features. coreboot is not yet able to make use of these two signals.
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- `SB_PWR` lights up whenever board is receiving power. It's all hardware
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and does not concern coreboot.
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- `DRCT` is an undocumented 2-pin header next to the front panel connector block. It
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connects to both the power button circuit and Z77's intruder detection input. Shorting this
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header triggers both. With coreboot it currently works the same as the power button.
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## Extra exposed GPIOs at `TB_HEADER`
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A number of GPIO lines are broken out to `TB_HEADER` to support the ThunderboltEX adapter,
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which never took off. Now they're yours to play with. Additional programming may be required such
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as enabling GPIO by I/O for maximum effect.
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This may be safely ignored for most normal uses.
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**Be careful not to apply more than 3.3v to these pins!** And do not touch the two pins
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labeled "NOT A GPIO".
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Pinout:
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```
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+---+---+---+---+---+
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| 2 | 4 | 5 | 7 | 9 |
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+---+---+---+---+---+
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| 1 | 3 | | 6 | 8 |
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+---+---+---+---+---+
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```
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```{eval-rst}
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+-----+-----------------------+----------+--------+
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| Pin | Name | Source | GPIO # |
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+=====+=======================+==========+========+
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| 1 | S_DP_DDC_CLK_TO_TB | **NOT A GPIO** |
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+-----+-----------------------+----------+--------+
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| 2 | TB_GPIO_6 | NCT6779D | 14 |
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+-----+-----------------------+----------+--------+
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| 3 | S_DP_DDC_DATA_TO_TB | **NOT A GPIO** |
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+-----+-----------------------+----------+--------+
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| 4 | TB_GPIO_7 | NCT6779D | 13 |
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+-----+-----------------------+----------+--------+
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| 5 | TB_FWUPDATE | NCT6779D | 11 |
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+-----+-----------------------+----------+--------+
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| 6 | TB_DEV_HPD | Z77 | 0 |
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+-----+-----------------------+----------+--------+
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| 7 | TB_GO2SX | NCT6779D | 17 |
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+-----+-----------------------+----------+--------+
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| 8 | TB_GO2SX#_ACK | NCT6779D | 16 |
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+-----+-----------------------+----------+--------+
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| 9 | Not connected |
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+-----+-------------------------------------------+
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```
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Pins 2, 4, 6, 8 have 1M ohm pulldowns.
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## Technology
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```{eval-rst}
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6779D |
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+------------------+--------------------------------------------------+
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| EC | TPU (ENE KB3722), AI1314 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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- [Flash chip datasheet][W25Q64FVA1Q]
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[ASUS P8Z77-V LE PLUS]: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/
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[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[rtnicpg]: https://github.com/redchenjs/rtnicpg
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@ -53,6 +53,7 @@ P8H77-V <asus/p8h77-v.md>
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P8Z77-M <asus/p8z77-m.md>
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P8Z77-M Pro <asus/p8z77-m_pro.md>
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P8Z77-V <asus/p8z77-v.md>
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P8Z77-V LE PLUS <asus/p8z77-v_le_plus.md>
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wifigo_v1 <asus/wifigo_v1.md>
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```
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@ -58,6 +58,15 @@ config BOARD_ASUS_P8Z77_M
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select SUPERIO_NUVOTON_NCT6779D
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select SUPERIO_NUVOTON_COMMON_COM_A
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config BOARD_ASUS_P8Z77_V_LE_PLUS
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select BOARD_ASUS_P8X7X_SERIES
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select BOARD_ROMSIZE_KB_8192
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select RT8168_SET_LED_MODE
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select SUPERIO_NUVOTON_NCT6779D
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select USE_NATIVE_RAMINIT
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select POWER_LED_USES_GPIO8
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select HAVE_SHARED_PS2_PORT
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if BOARD_ASUS_P8X7X_SERIES
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config POWER_LED_USES_GPIO8
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@ -75,6 +84,7 @@ config VARIANT_DIR
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default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
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default "p8z77-v" if BOARD_ASUS_P8Z77_V
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default "p8z77-m" if BOARD_ASUS_P8Z77_M
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default "p8z77-v_le_plus" if BOARD_ASUS_P8Z77_V_LE_PLUS
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config MAINBOARD_PART_NUMBER
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default "P8C WS" if BOARD_ASUS_P8C_WS
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@ -83,6 +93,7 @@ config MAINBOARD_PART_NUMBER
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default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
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default "P8Z77-V" if BOARD_ASUS_P8Z77_V
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default "P8Z77-M" if BOARD_ASUS_P8Z77_M
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default "P8Z77-V LE PLUS" if BOARD_ASUS_P8Z77_V_LE_PLUS
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -17,3 +17,6 @@ config BOARD_ASUS_P8Z77_V
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config BOARD_ASUS_P8Z77_M
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bool "P8Z77-M"
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config BOARD_ASUS_P8Z77_V_LE_PLUS
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bool "P8Z77-V LE PLUS"
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://www.asus.com/supportonly/p8z77-v%20le%20plus/helpdesk_manual/
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2012
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@ -0,0 +1,12 @@
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## SPDX-License-Identifier: GPL-2.0-only
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boot_option=Fallback
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gfx_uma_size=64M
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debug_level=Debug
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nmi=Disable
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power_on_after_fail=Disable
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sata_mode=AHCI
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gfx_uma_size=64M
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audio_panel_type=HDA
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spdif_dest=SPDIF_OUT
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pciex16_3_bandwidth=x2
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@ -0,0 +1,102 @@
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 4 power_on_after_fail
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411 2 e 5 sata_mode
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# coreboot config options: northbridge
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416 5 e 6 gfx_uma_size
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# coreboot config options: mainboard
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425 1 e 9 audio_panel_type
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426 1 e 10 spdif_dest
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427 1 e 11 pciex16_3_bandwidth
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# coreboot config options: check sums
|
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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||||
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enumerations
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#ID value text
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|
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# Generic on/off enum
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1 0 Disable
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1 1 Enable
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# boot_option
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2 0 Fallback
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2 1 Normal
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# debug_level
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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|
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# power_on_after_fail
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4 0 Disable
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4 1 Enable
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4 2 Keep
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|
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# sata_mode
|
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5 0 AHCI
|
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5 1 Compatible
|
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5 2 Legacy
|
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|
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# gfx_uma_size (Intel IGP Video RAM size)
|
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6 0 32M
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6 1 64M
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6 2 96M
|
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6 3 128M
|
||||
6 4 160M
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||||
6 5 192M
|
||||
6 6 224M
|
||||
6 7 256M
|
||||
6 8 288M
|
||||
6 9 320M
|
||||
6 10 352M
|
||||
6 11 384M
|
||||
6 12 416M
|
||||
6 13 448M
|
||||
6 14 480M
|
||||
6 15 512M
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||||
6 16 1024M
|
||||
|
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# audio_panel_type
|
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9 0 HDA
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||||
9 1 AC97
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|
||||
# spdif_dest
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10 0 SPDIF_OUT
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10 1 HDMI
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|
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# pciex16_3_bandwidth
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11 0 x2
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11 1 x4
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||||
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||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 423 984
|
||||
Binary file not shown.
|
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <cf9_reset.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <superio/nuvoton/nct6779d/nct6779d.h>
|
||||
#include <southbridge/intel/common/rcba.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <console/console.h>
|
||||
#include <option.h>
|
||||
|
||||
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
|
||||
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
|
||||
#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V)
|
||||
|
||||
enum pciex16_3_bandwidth {
|
||||
PCIEX16_3_X2 = 0,
|
||||
PCIEX16_3_X4 = 1
|
||||
};
|
||||
|
||||
void mainboard_late_rcba_config(void)
|
||||
{
|
||||
/* This is called after raminit. We turn off DRAM_LED here. */
|
||||
nuvoton_pnp_enter_conf_state(GPIO0_DEV);
|
||||
pnp_set_logical_device(GPIO0_DEV);
|
||||
pnp_write_config(GPIO0_DEV, 0xe1, 0x80);
|
||||
nuvoton_pnp_exit_conf_state(GPIO0_DEV);
|
||||
|
||||
DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
|
||||
DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
|
||||
DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
|
||||
DIR_ROUTE(D26IR, PIRQH, PIRQF, PIRQC, PIRQD);
|
||||
DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
|
||||
DIR_ROUTE(D22IR, PIRQF, PIRQD, PIRQC, PIRQB);
|
||||
}
|
||||
|
||||
void bootblock_mainboard_init(void)
|
||||
{
|
||||
int gp46 = 0;
|
||||
|
||||
/*
|
||||
* PCHSTRP9[PCIEPCS1] soft strap (reflected here) tells us how PCIe lanes 1-4 are
|
||||
* configured.
|
||||
*
|
||||
* GPIO46 controls one ASM1440 switch that routes PCH PCIe lanes 3 & 4 as follows:
|
||||
* 0 = PCIEX1_1 and PCIEX1_2 respectively (pulled low on board)
|
||||
* 1 = PCIEX16_3
|
||||
*/
|
||||
u8 pciepcs1 = RCBA32(RPC) & 0x3;
|
||||
/*
|
||||
unsigned int pciex16_bandwidth = get_uint_option("pciex16_3_bandwidth", PCIEX16_3_X2);
|
||||
u8 new_pciepcs1 = (pciex16_bandwidth == PCIEX16_3_X4) ? 3 : 1;
|
||||
|
||||
if (pciepcs1 != new_pciepcs1) {
|
||||
printk(BIOS_INFO, "Updating PCHSTRP9[PCIEPCS1] to 0x%x... ", new_pciepcs1);
|
||||
if (write_pchstrp9(new_pciepcs1)) {
|
||||
printk(BIOS_INFO, "done.\n");
|
||||
full_reset();
|
||||
} else {
|
||||
*/
|
||||
/* Strap update failed.
|
||||
* If halting, blink PCH GPIO8 for power LED so that this condition
|
||||
* can be indicated by DRAM_LED lit and power LED blinking.
|
||||
* If not, need a way to let user know to restore
|
||||
* the flash descriptor with flashrom. System may be unstable.
|
||||
*/
|
||||
/*printk(BIOS_ERR, "PCH soft strap update failed!\n");
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
switch (pciepcs1) {
|
||||
case 1: /* 1 x2, 3/4 x1 */
|
||||
break;
|
||||
case 3: /* 1 x4 */
|
||||
gp46 = 1;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "PCH PCIe lane configuration 0x%x is invalid!\n", pciepcs1);
|
||||
}
|
||||
|
||||
/* Match GPIO to soft strap. */
|
||||
set_gpio(46, gp46);
|
||||
}
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
|
||||
|
||||
/* Select SIO pin states */
|
||||
pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
|
||||
pnp_write_config(GLOBAL_DEV, 0x27, 0x10);
|
||||
pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
|
||||
pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
|
||||
|
||||
/* Power RAM in S3 */
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, 0x10);
|
||||
|
||||
/* Turn on DRAM_LED. If raminit dies, this would remain on and we know
|
||||
* we have a problem. We turn it off after raminit. */
|
||||
pnp_set_logical_device(GPIO0_DEV);
|
||||
pnp_write_config(GPIO0_DEV, 0x30, 0x02);
|
||||
pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
|
||||
pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
|
||||
|
||||
nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
|
||||
|
||||
/* Enable UART */
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* Put PCIe root port 6 into subtractive decode. This should allow a POST card in
|
||||
* the PCI slot to receive POST codes via a connected ASM1083 bridge.
|
||||
*
|
||||
* TODO: Also needs to set up early PCI bridge.
|
||||
*/
|
||||
if (CONFIG(POST_DEVICE_PCI_PCIE)) {
|
||||
pci_or_config32(PCI_DEV(0, 30, 0), 0x4c, 1 << 28); /* pci_bridge[BPC] |= SDE */
|
||||
pci_write_config32(PCH_PCIE_DEV(5), 0xec, 1); /* pcie_rp6[PECR3] |= SDE */
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP1,
|
||||
HDMI1,
|
||||
HDMI2,
|
||||
HDMI3,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
206
src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c
Normal file
206
src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/gpio.c
Normal file
|
|
@ -0,0 +1,206 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO, /* SMI# of ASM1042 USB3 */
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
.gpio3 = GPIO_MODE_GPIO,
|
||||
.gpio4 = GPIO_MODE_GPIO,
|
||||
.gpio5 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO, /* PCIEX16_3 card presence, active low */
|
||||
.gpio8 = GPIO_MODE_GPIO, /* Power LED */
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO, /* ME_UNLOCK (Set high to unlock SPI descriptor) */
|
||||
.gpio28 = GPIO_MODE_GPIO, /* S_IVR_EN */
|
||||
.gpio29 = GPIO_MODE_GPIO, /* EC_SPI_WP# */
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO, /* AI1314 BCS1 */
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio2 = GPIO_DIR_INPUT,
|
||||
.gpio3 = GPIO_DIR_INPUT,
|
||||
.gpio4 = GPIO_DIR_INPUT,
|
||||
.gpio5 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio11 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_INPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio19 = GPIO_DIR_INPUT,
|
||||
.gpio20 = GPIO_DIR_INPUT,
|
||||
.gpio21 = GPIO_DIR_INPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio23 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_INPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio8 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
.gpio31 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio27 = GPIO_RESET_RSMRST
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio11 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_GPIO, /* EPU switch, active low */
|
||||
.gpio45 = GPIO_MODE_GPIO, /* TPU switch, active low */
|
||||
.gpio46 = GPIO_MODE_GPIO, /* QSWU1 (High = PCH PCIe lanes 3/4 goes to PCIEX16_3) */
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO, /* AI1314 BCS0 */
|
||||
.gpio58 = GPIO_MODE_GPIO,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
.gpio61 = GPIO_MODE_GPIO,
|
||||
.gpio62 = GPIO_MODE_GPIO,
|
||||
.gpio63 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_INPUT,
|
||||
.gpio33 = GPIO_DIR_INPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio44 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_OUTPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_INPUT,
|
||||
.gpio52 = GPIO_DIR_INPUT,
|
||||
.gpio53 = GPIO_DIR_INPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio55 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_OUTPUT,
|
||||
.gpio58 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_INPUT,
|
||||
.gpio61 = GPIO_DIR_INPUT,
|
||||
.gpio62 = GPIO_DIR_INPUT,
|
||||
.gpio63 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio46 = GPIO_LEVEL_LOW, /* Needs to be set at runtime */
|
||||
.gpio57 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
.gpio46 = GPIO_RESET_RSMRST,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_GPIO,
|
||||
.gpio65 = GPIO_MODE_GPIO,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO, /* RTL8111 ISOLATE# */
|
||||
.gpio69 = GPIO_MODE_GPIO, /* A BIOS flashback signal */
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO, /* WP# of main SPI flash chip */
|
||||
.gpio74 = GPIO_MODE_GPIO,
|
||||
.gpio75 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio64 = GPIO_DIR_INPUT,
|
||||
.gpio65 = GPIO_DIR_INPUT,
|
||||
.gpio68 = GPIO_DIR_OUTPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_OUTPUT,
|
||||
.gpio74 = GPIO_DIR_INPUT,
|
||||
.gpio75 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio68 = GPIO_LEVEL_HIGH,
|
||||
.gpio72 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
#include <option.h>
|
||||
|
||||
/* Shorthands */
|
||||
#define AZALIA_PIN_REAR(dev, color, misc, association, sequence) \
|
||||
AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_REAR, dev, AZALIA_STEREO_MONO_1_8, \
|
||||
color, misc, association, sequence)
|
||||
#define AZALIA_PIN_FRONT(dev, color, misc, association, sequence) \
|
||||
AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_FRONT, dev, AZALIA_STEREO_MONO_1_8, \
|
||||
color, misc, association, sequence)
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0889, /* Realtek ALC889 */
|
||||
0x1043841a, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x1043841a),
|
||||
AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
AZALIA_ATAPI,
|
||||
AZALIA_SPDIF_OUT,
|
||||
AZALIA_ATAPI_INTERNAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
3, 0)), /* SPDIF out 2, 0x99430130 */
|
||||
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_REAR(
|
||||
AZALIA_LINE_OUT,
|
||||
AZALIA_GREEN,
|
||||
0,
|
||||
1, 0)), /* 0x01014010 */
|
||||
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_REAR(
|
||||
AZALIA_LINE_OUT,
|
||||
AZALIA_BLACK,
|
||||
0,
|
||||
1, 2)), /* 0x01011012 */
|
||||
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_REAR(
|
||||
AZALIA_LINE_OUT,
|
||||
AZALIA_ORANGE,
|
||||
0,
|
||||
1, 1)), /* 0x01016011 */
|
||||
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_REAR(
|
||||
AZALIA_LINE_OUT,
|
||||
AZALIA_GREY,
|
||||
0,
|
||||
1, 4)), /* 0x01012014 */
|
||||
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_REAR(
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_PINK,
|
||||
8,
|
||||
5, 0)), /* 0x01a19850 */
|
||||
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_FRONT(
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_PINK,
|
||||
0xc,
|
||||
6, 0)), /* 0x02a19c60 */
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_REAR(
|
||||
AZALIA_LINE_IN,
|
||||
AZALIA_BLUE,
|
||||
0,
|
||||
5, 15)), /* 0x0181305f */
|
||||
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_FRONT(
|
||||
AZALIA_HP_OUT,
|
||||
AZALIA_GREEN,
|
||||
0xc,
|
||||
2, 0)), /* 0x02214c20),*/
|
||||
AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), /* Beep */
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_REAR,
|
||||
AZALIA_SPDIF_OUT,
|
||||
AZALIA_OPTICAL,
|
||||
AZALIA_ORANGE,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
4, 0)), /* 0x01456140 */
|
||||
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
|
||||
|
||||
0x80862806, /* Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x58560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
enum e_spdif2_dest {
|
||||
SPDIF2_SPDIF_OUT = 0,
|
||||
SPDIF2_HDMI
|
||||
};
|
||||
|
||||
enum e_aafp {
|
||||
AAFP_HDA = 0,
|
||||
AAFP_AC97
|
||||
};
|
||||
|
||||
void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
|
||||
{
|
||||
/*
|
||||
* With vendor firmware, if audio front panel type is set as AC97, line out 2
|
||||
* (0x1b) and mic 2 (0x19) pins of ALC889 are configured differently.
|
||||
*
|
||||
* The differences are all in the "Misc" fields of configuration defaults (in byte 2)
|
||||
* as shown below. Datasheet did not offer details on what those bits
|
||||
* (listed as reserved in HDA spec) are, so we'll have to take their word for it.
|
||||
*
|
||||
* Pin | 0x19 | 0x1b
|
||||
* -----+------+-----
|
||||
* HDA | 1100 | 1100
|
||||
* AC97 | 1001 | 0001
|
||||
*/
|
||||
const u32 front_aafp_verbs[] = {
|
||||
AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99),
|
||||
AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41)
|
||||
};
|
||||
|
||||
/* If user chooses to have digital audio out 2 to go on the HDMI port,
|
||||
* reprogram this pin as such:
|
||||
*
|
||||
* AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC(
|
||||
* AZALIA_JACK,
|
||||
* AZALIA_DIGITAL_DISPLAY,
|
||||
* AZALIA_DIGITAL_OTHER_OUT,
|
||||
* AZALIA_OTHER_DIGITAL,
|
||||
* AZALIA_BLACK,
|
||||
* AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
* 3, 0))
|
||||
*
|
||||
* Coded this way because we don't need to reprogram byte 0.
|
||||
*/
|
||||
const u32 spdif_to_hdmi_verbs[] = {
|
||||
AZALIA_VERB_12B(0, 0x11, 0x71f, 0x18),
|
||||
AZALIA_VERB_12B(0, 0x11, 0x71e, 0x56),
|
||||
AZALIA_VERB_12B(0, 0x11, 0x71d, 0x11)
|
||||
};
|
||||
|
||||
if (viddid == 0x10ec0889) {
|
||||
if (get_uint_option("audio_panel_type", AAFP_HDA) == AAFP_AC97) {
|
||||
azalia_program_verb_table(base, front_aafp_verbs,
|
||||
ARRAY_SIZE(front_aafp_verbs));
|
||||
}
|
||||
if (get_uint_option("spdif_dest", SPDIF2_SPDIF_OUT) == SPDIF2_HDMI) {
|
||||
azalia_program_verb_table(base, spdif_to_hdmi_verbs,
|
||||
ARRAY_SIZE(spdif_to_hdmi_verbs));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/intel/sandybridge
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x84ca inherit
|
||||
device ref peg11 on # PCIEX_16_2
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthLong" "PCIEX16_2" "SlotDataBusWidth8X"
|
||||
end
|
||||
chip southbridge/intel/bd82x6x
|
||||
register "usb_port_config" = "{
|
||||
{ 1, 2, 0 },
|
||||
{ 1, 8, 0 },
|
||||
{ 1, 8, 1 },
|
||||
{ 1, 8, 1 },
|
||||
{ 1, 9, 2 },
|
||||
{ 1, 9, 2 },
|
||||
{ 1, 0xa53, 3 },
|
||||
{ 1, 0xa53, 3 },
|
||||
{ 1, 0xa53, 4 },
|
||||
{ 1, 0xa53, 4 },
|
||||
{ 1, 0xa53, 6 },
|
||||
{ 1, 0xa53, 5 },
|
||||
{ 1, 0xa53, 5 },
|
||||
{ 1, 0xa53, 6 }
|
||||
}"
|
||||
register "gen1_dec" = "0x000c0291" # NCT6779 HWM
|
||||
register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC
|
||||
|
||||
device ref pcie_rp1 on # PCIEX_16_3 (electrical x2 or x4)
|
||||
smbios_slot_desc "SlotTypePciExpressGen2X4" "SlotLengthLong" "PCIEX16_3" "SlotDataBusWidth4X"
|
||||
end
|
||||
device ref pcie_rp3 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_1" "SlotDataBusWidth1X"
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "PCIEX1_2" "SlotDataBusWidth1X"
|
||||
end
|
||||
device ref pcie_rp5 on # RTL8111F LAN
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x482"
|
||||
device pci 00.0 on
|
||||
subsystemid 0x1043 0x8505
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 on # ASM1083 PCI bridge
|
||||
subsystemid 0x1043 0x8489
|
||||
smbios_slot_desc "SlotTypePci" "SlotLengthLong" "PCI1" "SlotDataBusWidth32Bit"
|
||||
end
|
||||
device ref pcie_rp7 on # Marvell 88SE9120 ESATA6G
|
||||
subsystemid 0x1043 0x83ba
|
||||
end
|
||||
device ref pcie_rp8 on # ASM1042 USB3
|
||||
subsystemid 0x1043 0x8488
|
||||
end
|
||||
device ref hda on
|
||||
subsystemid 0x1043 0x841a
|
||||
end
|
||||
device ref lpc on
|
||||
chip superio/nuvoton/nct6779d
|
||||
device pnp 2e.1 off end # Parallel
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off end # UART B, IR
|
||||
device pnp 2e.5 on # PS2 KBC
|
||||
io 0x60 = 0x0060 # KBC1 base
|
||||
io 0x62 = 0x0064 # KBC2 base
|
||||
irq 0x70 = 1 # Keyboard IRQ
|
||||
irq 0x72 = 12 # Mouse IRQ
|
||||
# KBC 12Mhz/A20 speed/sw KBRST
|
||||
drq 0xf0 = 0x82
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GPIOs 6-8
|
||||
device pnp 2e.8 off end # WDT1 GPIO 0-1
|
||||
device pnp 2e.108 on end # GPIO0
|
||||
device pnp 2e.109 on end # GPIO1
|
||||
device pnp 2e.509 on end # GPIO5 all in
|
||||
device pnp 2e.a on # ACPI
|
||||
drq 0xe7 = 0x11
|
||||
drq 0xf2 = 0x5d # Enable PME
|
||||
end
|
||||
device pnp 2e.b on # H/W Monitor, FP LED
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0
|
||||
irq 0x70 = 0
|
||||
drq 0xe4 = 0xf9 # Use GP50/52/55
|
||||
end
|
||||
device pnp 2e.d off end # WDT1
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f off end
|
||||
device pnp 2e.14 on end # Port 80 UART
|
||||
device pnp 2e.16 off end # Deep sleep
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue