This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.
BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
coreboot displays the following log:
CPU: ID c06c3, Pantherlake B0, ucode: 0000010c
Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change introduces `LB_TAG_BOOT_MODE` to the coreboot tables to
convey platform boot information to the payload. The new `lb_boot_mode`
struct uses `enum boot_mode_t` to specify whether the device is booting
in `normal mode`, `low-battery mode` or `off-mode charging`.
This is crucial for platforms where the Application Processor (AP)
manages the charging solution, as it provides the necessary context for
the payload's charger driver. By passing this data through the coreboot
table, we avoid redundant implementation and ensure consistent battery
and charging information is available across both coreboot and the
payload.
A new weak function, `lb_add_boot_mode`, is also introduced. This
function can be overridden by platforms that require this data to add
the boot mode information to the coreboot table.
TEST=Able to build and boot google/quenbi.
Change-Id: I5aea72c02b4d6c856e2504f4007de584c59ee89f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This is a purely cosmetic change to make things slightly more easier to
read. We also only add the IDs which are actively used in the codebase.
TEST=Timeless build produces identical binaries
Change-Id: I4ec0a570020059c85768bab913dff1ba1977e9f9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88917
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This patch makes DRAM an explicit region by introducing
DECLARE_OPTIONAL_REGION(dram) and DRAM_END().
Note: many SoC platforms determine DRAM size and layout dynamically
during boot, making a static compile-time value is not feasible always.
Attempting to use REGION_SIZE(dram) in this scenario would result in a
missing symbol `_dram_size` error.
By making dram an optional region, we allow its size and address to be
defined only when available, preventing build failures on platforms
that configure DRAM dynamically.
The old extern u8 _dram[] is removed, as it's now covered by the new
region definition.
This is a preparatory step for future changes that will make use of
the new DRAM_END() macro.
This symbol is necessary for systems that require
the DRAM size to be known and accessible from the linker script or
other parts of the build system.
Additionally, a new macro DRAM_END(addr) is defined in memlayout.h.
This macro provides a consistent way to mark the end of the DRAM
region, similar to how REGION_END and other start/end macros are used
throughout the codebase.
TEST=Able to build and boot google/quenbi.
Change-Id: Ib98ec4b991eed56385c83be6a9ca39ff1380ff1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce cbfs_preload_wait_for_all() to guarantee that all CBFS preload
contexts complete their tasks before moving forward. This function goes
through each preload context and waits for the corresponding thread to
finish by using thread_join(). If any preload thread runs into an issue,
it records an error message along with the context name.
This addition provides a synchronization point during the boot process
which platform code can leverage, typically when the storage backend
supporting asynchronous file transfer is about to be deactivated.
Change-Id: I3ee27ef2fbfdc19bd75532713966f333ad975861
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88457
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently .bss and .data are within the PT_LOAD area of the
bootblock.elf and thus are placed and initialized at the correct spot
when PSP loads the BIOS Reset Image into DRAM.
On S3 resume PSP verifies that the "BIOS Reset Image" is unmodified
before it hands over control to such. Due to the use of BSS and DATA
within the BIOS Reset Image and the modifications of such at previous
boot the verification always fails.
This change moves '.bss' and '.data' out of the *first* PT_LOAD area
and moves it into a separate data_segment also marked PT_LOAD. Since
the second PT_LOAD is ignored by AMDCOMPRESS it doesn't end in the area
being verified at S3 resume. Since '.data' is now part of a separate
PT_LOAD a new region is inserted called '.datacopy' which is filled
by using objcopy. In turn the assembly code in bootblock will memcpy
'.datacopy' to '.data'.
TEST: Can still boot on amd/birman+ and on up/squared.
Change-Id: Id159ade3029060ce2ca6abcb723d5bdfe8841c3a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
permanent_smi_handler and acpi_s3_resume_allowed returns boolean,
so use boolean instead of int.
Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.
We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.
Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the `SPLASH_SCREEN_FOOTER` Kconfig option,
enabling a custom footer image or logo on the firmware splash screen.
This provides an additional branding opportunity for device
manufacturers.
`soc_load_logo_by_coreboot()` now conditionally loads and renders
`footer_logo.bmp` when this option is enabled. The footer logo is
positioned at the bottom of the screen.
A new `SPLASH_SCREEN_FOOTER_LOGO_PATH` Kconfig option is added to
define the footer logo's file path. It defaults to a mainboard-specific
location. `Makefile.mk` is updated to ensure this logo is included in
the CBFS.
This additional branding is made possible by rendering bitmaps using
coreboot's native implementation (`USE_COREBOOT_FOR_BMP_RENDERING`).
FSP currently lacks the necessary callbacks to support this feature.
Currently, the OEM footer branding will appear even when the
system is booting in low-battery mode. A planned update will fix this
by exiting early from the boot process, preventing the footer from
showing and conserving power.
BUG=b:423591644
TEST=Able to display custom footer logo on boot.
Change-Id: I57f8af910e8b8f56e8a4a88f8cca6d60fad380b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces `bmp_load_logo_by_type()` to allow loading a
specific BMP logo from CBFS based on `enum bootsplash_type`.
Now, bmp_load_logo() leverages bmp_load_logo_by_type() with the
system-determined logo type. The new bmp_load_logo_by_type() function
provides a direct interface to load any specified BMP by `enum
bootsplash_type`, which is beneficial for scenarios requiring explicit
logo selection.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. Ensure FW splash screen looks
proper.
Change-Id: I2473f7d48ca2d196ced89d81391cf387627a2f86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88013
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an enumerated type `bootsplash_type` to
differentiate between various bootsplash logos, such as
`BOOTSPLASH_LOW_BATTERY` and `BOOTSPLASH_CENTER`.
A `bootsplash_list` array is added to map these types to their
corresponding default filenames. A new function,
`bmp_get_logo_filename`, is provided to retrieve the correct logo
filename based on the specified bootsplash type. This function also
handles overriding the `BOOTSPLASH_CENTER` logo name if
`CONFIG(HAVE_CUSTOM_BMP_LOGO)` is enabled.
The `bmp_load_logo` function is updated to utilize the new
`bootsplash_type` and `bmp_get_logo_filename` to dynamically select the
appropriate logo for display. This change streamlines logo management
and improves flexibility for different boot scenarios.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.
Change-Id: I882deda56b5d30bb15cc7def408c4ea479ffd6ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The definitions added are based on the following reference documents:
1. Document #815002 Panther Lake H External Design Specification
Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6
Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This ensures that bridge windows allocate enough space to cover
SR-IOV BARs. Without this Linux will print messages, these messages
may differ depending on the kernel version used.
Debian GNU/Linux 12 (kernel 6.1.0-28-amd64):
pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref]
pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit
pref]
Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic):
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't
assign; no space
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to
assign
TEST=Raptorlake-P
Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34620
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add IDs from the EDS, with a couple extras:
- eSPI: EDS says 0x7202, but our boards show 0x7702
- GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed
Change-Id: I8430914edd02954cbb38592bff896733b01c735d
Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Currently the SMMSTOREv2 only supports MMIO ROM below 4GiB. As the
space below 4GiB is typically limited on x86, add support for extended
MMIO ROM windows as found on recent hardware.
Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new
field to the coreboot table called 'mmap_addr'. The users outside
of coreboot must check the size field of the coreboot struct to
determine if mmap_addr is supported. When it is it holds the
64-bit physical address to the MMIO ROM window.
The old 'mmap_addr' was renamed to 'mmap_addr_deprecated' to indicate
that it should not be used any more.
Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87114
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This change refactors MTRR handling by consolidating helper functions
from `earlymtrr.c` and `mtrr.c` into a new MTRR library (`mtrrlib`).
This approach improves code modularity and reusability, making these
utilities consistently available across different coreboot boot phases.
The following functions are now part of `mtrrlib`:
- `get_free_var_mtrr`: Retrieves the index of the first available
variable MTRR.
- `set_var_mtrr`: Configures the variable MTRR, specified by an `index`,
for a memory region defined by `base`, `size`, and `type`.
- `clear_var_mtrr`: Disables the variable MTRR at a given index.
- `acquire_and_configure_mtrr`: Acquires a free variable MTRR, configures
it with the given `base`, `size`, and `type`.
BUG=b:409718202
TEST=Built and booted google/fatcat successfully.
Change-Id: Iba332b7088221fd930e973fad9410833bff184b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87539
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Currently there are 3 GDTs (Global Descriptor Tables) being used on x86:
- preRAM (gdt_init.S)
- SMM (smm_stub.S)
- RAM (c_start.S)
They have different layouts and thus different offsets for the segments
being used in assembly code. Stop using different GDT segments and
ensure that for ROM (preRAM + SMM) and RAM (ramstage) the segments
match. RAM will have additional entries, not found in pre RAM GDT,
but the segments for protected mode and 64-bit mode now match in
all stages.
This allows to use the same defines in all stages. It also drops the
need to know in which stage the code is compiled and it's no longer
necessary to switch the code segment between stages.
While at it fix the comments in the ramstage GDT and drop unused
declarations from header files, always set the accessed bit and drop
GDT_CODE_ACPI_SEG.
Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add a header with a CFR object for setting the coreboot console log
level, so that all mainboards can make use of it without duplication.
Change-Id: I473421e0e6b2031eb9846f5a798b427104dc3af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
For simplicity we are going to impose this restriction to coreboot.
Note however that this is only a restriction for coreboot itself. The
FMAP tool itself is still a generic tool that does not require the FMAP
to start at offset 0.
Add an defacto empty fmap_config.h to our test cases, since fmap.h now
includes fmap_config.h.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba04ebdcd5557664a865d2854028dd811f052249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This reverts commit 4b5a490b6f.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 6b446b991b.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.
BUG=NA
TEST=Customer platform with Raptorlake-P
Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Intel processor number X7433RE.
Based on docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Update SoundWire driver to support ALC712 audio codec.
reference datasheet: Realtek ALC712-VB-CG Rev. 0.24
BUG=b:378629979
TEST=emerge-fatcat coreboot
A sound can be heard from the speaker,
the test instructions are as follows:
amixer -c 0 cset name='rt712 OT23 L Switch' on
amixer -c 0 cset name=''rt712 OT23 R Switch' on
amixer -c 0 cset name='rt1320-1 OT23 L Switch' on
amixer -c 0 cset name='rt1320-1 OT23 R Switch' on
amixer -c 0 cset name='Speaker Switch' on
speaker-test -D hw:0,2 -c 2 -t sine -f 440
Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move
them to common header src/include/cpu/amd/msr.h
Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
AMD64 spec refers to the field as MT (Message Type), but the IA64 spec
refers to it as DM (Delivery Mode). The problem is that there is another
field abbreviated as DM (Destination Mode) right next to it. So for
better readability, just stick to the AMD64 terminology.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.
But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
RISC-V doesn't support unaligned access, so check for that before
decoding and encoding. It is not perfectly performant, but still much
better then invoking the misaligned exception handler every time there
is a misaligned access. We can't modify our whole codebase to always do
aligned access, because it is neither feasible in long term nor is fair
to add that performance penalty onto other architectures that do support
unaligned access. So this is the next best thing.
On architectures that do support unaligned access the compiler will just
optimize the RISCV_ENV part out and should result in the exact same
binary.
tested: identical binary on QEMU-aarch64 and QEMU-q35.
Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
No need for this to be a signed or unsigned int.
TEST=tested with rest of patch train.
Change-Id: I409c04b928211e0e89eec324fdf3fa3997c73576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86942
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Move PCI Option ROM handling code into device/pci_rom.c as it's
already using a majority of functions within this file.
Change-Id: I50fc3bf45a1ab6572ab031b9e24ca2f882a13aad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently the VBIOS is placed somewhere in DRAM when necessary.
While generating ACPI tables the code attempts to find the VBIOS
by looking at "known" places.
Simplify the code and keep track of the VBIOS using a pointer in
struct device by filling it in pci_rom_load().
The following patches will reuse this pointer to generalize the
code even more.
Change-Id: Ib27d30e3b07740d6098d4f7a5c4f5d8bce976f00
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.
Specifically, it:
- Moves Kconfig options related to low-battery notifications from
drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
