The RAM_CODE on Tegra can be used to determine SDRAM configuration type.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Change-Id: Ica770ed6089f6ff8c38841f2cc8fd2778b6d786f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183781
Reviewed-by: Julius Werner <jwerner@chromium.org>
To avoid throttling at low temps raise the passive threshold
to 60C until things are better calibrated.
Also add a dependency for the charger participant to the thermal
relationship table so when it is enabled it will be used properly.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF application
Change-Id: I4b50eff6a019b1cab0c781962a94c069ddbf0727
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184008
These GPIOs are defined in the mainboard and will be returned
as part of the LPE Device _CRS method.
BUG=chrome-os-partner:24380
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I7fe0852b63499530f6dfef4553e818e7364f4101
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184007
This adds an ACPI Device entry for the LPE Audio controller
and code to put the device in ACPI mode if set in devicetree.cb
The ACPI device attempts to append GPIOs that may be defined in
the mainboard-supplied ACPI code.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: Build and boot on rambi with LPE in ACPI mode.
Without kernel support this is not very useful but it did show
that the device was no longer visible as a PCI device.
Change-Id: I44d5423f5bbea77e156012c071df6cb335fe658b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
792MHz BCT is from the board manuf, but boots fine on my
nyan. 924 BCT will be added later, when available.
BUG=none
TEST=builds and boots OK on my nyan board with depthcharge
changes for board id 0 in nyan_big.
BRANCH=none
Change-Id: I35f04dd7520ed9471287b2ecdbc1f0508bd78b6c
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183975
Reviewed-by: David Hendricks <dhendrix@chromium.org>
PMIC VDD_CPU voltage is always 1.2V, so skip board_id check.
204MHz BCT is from the board manuf, but boots fine on my
nyan. 792/924 BCTs will be added later, when available.
BUG=none
TEST=builds and boots OK on my nyan board with depthcharge
changes for board id 0 in nyan_big.
BRANCH=none
Change-Id: Ib26bed66414b4a0943f3cfd5de907d7135a69152
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183939
Reviewed-by: David Hendricks <dhendrix@chromium.org>
To support memory initialization without BootROM (which allows better
customization, updatable DRAM init procedure, and supporting more SDRAM
configurations that BootROM cannot handle), a new function "sdram_init(param)"
is introduced.
The input must be a "struct sdram_params", which has exactly the same layout as
the SDRAM fields in standard BCT file.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # Boots successfully
Change-Id: I36a26fb5236eee8f329e3f84cbdcc1ec6992fe6b
Reviewed-on: https://chromium-review.googlesource.com/182615
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
The new clock_sdram(...) initialized PLLM by given configuration (which needs to
be explicitly determined, usually from BCT or SDRAM parameters).
BUG=none
TEST=emerge-nyan chromeos-coreoot-nyan
# With other patches, the new function starts PLLM in correct clock.
Change-Id: I606d0506c734d312db9e1b72a910700ca766f2d3
Reviewed-on: https://chromium-review.googlesource.com/183621
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
This is a cpu supported by the foundation emulator. This will not build
at all without my cbfstool changes.
Not that our chromiumos qemu for x86 is months behind upstream.
BUG=None
TEST=breaks no builds
BRANCH=None
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Change-Id: I0e7df1a2d3801778e83c89ff18285b026403adc0
Reviewed-on: https://chromium-review.googlesource.com/180355
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
This change adds a header serialization function. Programmers can thus just
set up a header as needed, without worrying about forgetting if and how to
use the [hn]to[hn]* functions.
BUG=None
TEST=Build a peppy image and verify that it's bit for bit the same.
BRANCH=None
Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181552
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
BootROM uses RAM_CODE[3:2] value as index to retrieve boot device
array in BCT to reconfigure device. Since there will be one kind
of boot device, we can reuse RAM_CODE[3:2] in conjunction with
RAM_CODE[1:0] to select up to 16 RAM parameters. To support this
change without leading BootROM to read wrong boot device parameters,
we need to fill up boot device array.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully.
Change-Id: I901e052bc785561cfcb25fb24cf4629572af390a
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183833
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
The name snow goes by in many places in chromeos is daisy. Snow is technically
a variant of daisy and should really be called daisy_snow, but for historical
reasons the daisy board with no variant was used instead. To make it easier to
work with within chromeos, this change renames the snow board to daisy.
BUG=None
TEST=Built for daisy.
BRANCH=None
Change-Id: I569b31bf417db55be91832f15271bea4bc30f163
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183553
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The name pit goes by in many places in chromeos is peach_pit, where peach is
the base name and pit is the name of this particular variant. To make it
easier to work with within chromeos and to make the board names a little less
ambiguous, this change renames the pit board to peach_pit, and from Pit to
Peach Pit.
BUG=None
TEST=Built for peach_pit.
BRANCH=None
Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183552
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The nyan_big mainboard is very similar to nyan, but will be different in a few
ways. For instance, the BCT will be different, and the GPIOs may need to be
configured slightly differently.
This change also adds prefixes to the kconfig variables in "choice" blocks
for both boards since having multiple instances of choice blocks with the same
options confuses kconfig even if all of the instances have mutually exclusive
dependencies.
BUG=None
TEST=Built for nyan and nyan_big.
BRANCH=None
Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183532
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.
BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
and see it go away.
Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The GPIOs were not being put into SCI mode to enable
their respective interrupt lines as wake sources. Also
the bit index into the GPE block was incorrect. Fix
both of these issues.
BUG=chrome-os-partner:25251
BRANCH=baytrail
TEST=Noted the appropriate bit was enabled for wake.
Also was able to wake with the track pad.
Change-Id: Ia1b6e4c8cb4b012d76ad27a2158e28d183581025
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183598
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The _PRW method needs to specifcy a bit number within
the GPE block to enable wake events associated with a
given device. Therefore, add ACPI_ENABLE_WAKE_SUS_GPIO()
macro for the mainboards' convenience.
BUG=chrome-os-partner:25251
BRANCH=baytrail
TEST=On rambi used macros for touch pad and screen. Noted
the appropriate bit was enabled for wake. Also was
able to wake with the track pad.
Change-Id: I98d7c005997bdcaa3646fabec5199fbe013ca52c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This completes the improvements to the ELF file parsing code. We can
now parse section headers too, across all 4 combinations of word size
and endianness. I had hoped to completely remove the use of htonl
until I found it in cbfs_image.c. That's a battle for another day.
There's now a handy macro to create magic numbers in host byte order.
I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
we can use it for the others too, but this is sensitive code and
I'd rather change one thing at a time.
To maximize the ease of use for users, elf parsing is accomplished with
just one function:
int
elf_headers(const struct buffer *pinput,
Elf64_Ehdr *ehdr,
Elf64_Phdr **pphdr,
Elf64_Shdr **pshdr)
which requires the ehdr and pphdr pointers to be non-NULL, but allows
the pshdr to be NULL. If pshdr is NULL, the code will not try to read
in section headers.
BUG=None
TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same
BRANCH=None
Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181272
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
In order to boot from G3 quickly disable the
slp_x stretching policy.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I039de7990cc6ff519d873d64756c8d119b131165
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183588
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Provide an option for the mainboard to set in its devicetree
to disable slp_x stretching on SUS power well failure. This
will allow for fast G3->S0 transition instead of waiting for
1-4 seconds.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Enabled option. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I213525b3ad44fe4c95bfd014b614bbc80623cbb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183587
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable the PS2 mode for the VNN and VCC's
voltage regulator. It only gets enabled on
C0 and later parts.
BUG=chrome-os-partner:24542
BRANCH=baytrail
TEST=Built and booted b3.
Change-Id: Id96b5527227ec31da1e5cd106791fe45576b063b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183596
The VNN and VCC regulator for baytrail can enter
into PS2 mode under low power conditions to save
regulator power. This is available for >C0 parts.
Add a device tree option to enable PS2 for the
VCC and VNN rails.
BUG=chrome-os-partner:24542
BRANCH=baytrail
TEST=Built and booted b3.
Change-Id: Iea952b17ca77ac42f34285b2d171e566b755e002
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183595
The C0 cpuid's were added as well as the microcode, but we
weren't making C0 a first class citizen in the pattrs.
BUG=chrome-os-partner:24542
BRANCH=baytrail
TEST=Built and booted b3.
Change-Id: Ie23f8ce867f339eab3b55b8c5f49ab822f23eebb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The clocks for MEM(MC)/EMC should be either initialized by BootROM, or in the
step of SDRAM initialization. Changing their states in ramstage may cause
unexpected results (note MC even always ignores RESET states).
To make it clear, we should remove MEM/EMC from the clock initialization list.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully.
Change-Id: Icff9f78810ed5bd693b48d7b6d436ce2db919a5e
Reviewed-on: https://chromium-review.googlesource.com/183623
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
The EMC registers are required for memory initialization.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Change-Id: Ibfb35d5b3f44c97c2c36135110fa44996447734c
Reviewed-on: https://chromium-review.googlesource.com/183622
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
The EMC address was wrong and may cause memory initialization to fail.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Change-Id: Iaa8f21a6ba2d3850495da9a85711cf7fb7b09ad4
Reviewed-on: https://chromium-review.googlesource.com/183602
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
The Virtual Recovery switch flag needs to be set in coreboot since
it is passed through directly to VBOOT layer by depthcharge.
Rather than add a new config option we can assume that devices with
EC Software Sync also have a virtual recovery switch and set the
flag appropriately.
BUG=chrome-os-partner:25250
BRANCH=all
TEST=build and boot on rambi, successfully enter developer mode
Change-Id: Id067eacbc48bc25a86887bce8395fa3a9b85e9f2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The updated MRC wrapper allow the IO hole size to be
configured from the coreboot side of things.
BUG=None
BRANCH=baytrail
CQ-DEPEND=CL:*152595
TEST=Built and booted. Also changed io hole size from mainboard as test.
Change-Id: I7a626764aecce94bbaf35d884606480f22a9aa84
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183269
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This adds the very basic top-level support for determining the
system wake source from ACPI. It only implements the _SWS method
in the _SB scope which just returns a bit index into the PM1
status register for the first fixed functional block.
This can be used to determine wake source of RTC or Power Button
but does not help determine wake source for USB or GPIO.
The ACPI spec says to return -1 if no source can be determined
from PM1 status register.
BUG=chrome-os-partner:8127
BRANCH=baytrail
TEST=build and boot on rambi
1) Test resume from S3 by RTC:
ACPI System Wake Source is PM1 Index 10
(bit 10 is RTC_STS in ACPI spec, ACPI_EVENT_RTC in kernel)
2) Test resume from S3 by power button:
ACPI System Wake Source is PM1 Index 8
(bit 8 is PWRBTN_STS in ACPI spec, ACPI_EVENT_POWER_BUTTON in kernel)
3) Test resume from S3 by USB:
ACPI System Wake Source is PM1 Index -1
Change-Id: Ifc5c0867f82cf291af157537b8c13fe44923d8f5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are several things in GNVS being initialized in the
mainboard ACPI table creation step that are shared across all
boards using the chipset.
Move the init that is not board specific into a shared function
and call it from the table creation step.
BUG=chrome-os-partner:8127
BRANCH=baytrail
TEST=build and boot on rambi device
Change-Id: I178193d7fe298ec26247402370a1af9280bb09c1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183332
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update the microcode for c0 parts to 809.
BUG=None
BRANCH=baytrail
TEST=Built and booted on B3.
Change-Id: I733ce8eeae0b0eafe4a3a2dbeb09feba051c496a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183256
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The sdram_param.h from cbootimage has different type and #ifdef names that
should be changed to comply with Coreboot.
Note we also changed field names so it will be easier to cope with translating
BCT config file (*.cfg) into simple C structure definition.
BUG=none
TEST=none
Change-Id: I41fbc628da920863b4ae3d8795cb6dfe4fd31dca
Reviewed-on: https://chromium-review.googlesource.com/182614
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
A raw copy from NVIDIA cbootimage:
http://nv-tegra.nvidia.com/gitweb/?p=tools/cbootimage.git;\
a=blob;f=src/t124/nvboot_sdram_param_t124.h
This file containts required structure for initializing SDRAM.
BUG=none
TEST=none # The file is not used yet.
Change-Id: I580f7a86af84bc0fd8d88c4b59606893e73ea01c
Reviewed-on: https://chromium-review.googlesource.com/182613
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
To initialize memory without BootROM, we need more details in the PMC registers,
including "io_dpd3_req", "por_dpd_ctrl", and various mask values.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # successfully.
Change-Id: I5444e64f49a66320319a5c59ce14635364b74f39
Reviewed-on: https://chromium-review.googlesource.com/183231
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
To implement memory initialization without BCT, we need more details of memory
controller registers (mc).
Note some register names have been changed, so Nyan mainboard VPR code is also
modified.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # successfully.
Change-Id: I179aa41c5a6419fc94cc3343ff23080d1db19ca2
Reviewed-on: https://chromium-review.googlesource.com/182992
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
This blob is loaded by the kernel and is what runs immediately after resuming
from lp0. It turns on the main CPUs and returns control to them and runs on
the AVP. The directory is totally independent from coreboot and has its own
Makefile. The only external dependency is on the stdint.h header file. The
openssl command line utility is used to sign the blob. Its header is defined
in C and built as part of the image.
BUG=None
TEST=With changes to coreboot which save the SDRAM parameters for use by the
boot ROM, used this blob to suspend and resume using LP0. USB had to be
disabled because those drivers don't work across suspend and resume.
BRANCH=None
Change-Id: I056a1f9ad3fa333f5b1ca140c8b7be819ffa11c7
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183152
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
I messed up in setting this register, it should be using Tj_max-Temp
which in the default case works out to be 90-90=0.
This was apparently heavly throttling the CPU at idle temps.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, run graphics_WebGLPerformance test
Change-Id: I4338280cf50db84dc44313d6fb6771ea5af21dad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
These values are for the 2 and 4 core B-step parts.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=boot on rambi and check for valid GPU power values from DPTF
Change-Id: I2772cb9dbf17560fc31f871a111f32131c7e5105
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 701273892c7bdaf898a94a337fae9f7373a9c748)
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183102
This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.
BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946
Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Add support for initializing the rtc device. Also
add RTC well loss events to the eventlog and properly
clear the event so it doesn't get added again.
BUG=None
BRANCH=baytrail
TEST=Built and booted. Tested battery loss. Eventlog
has RTC event. In addition the rtc device can
be properly probed in the kernel resulting in
/sys/class/rtc/rtc0 being available.
Change-Id: I1ca608b069dc50db116d75963d5542a7f9b1811f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183051
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There's no reason to enable them, so keep them disabled to avoid
any unexpected behavior.
BUG=chrome-os-partner:24607
BRANCH=none
TEST=Built and booted on Nyan (rev1).
Change-Id: Ice7401b9986e6cc920356a3a5a082285c9b2f0a5
Reviewed-on: https://chromium-review.googlesource.com/181063
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
RAM_ID GPIOs were previously changed to GPIO_FUNC0 to configure for MMIO
access when legacy was the default. Now, MMIO is the default, so these
GPIOs can conform to the normal labeling scheme. This change should have
no functional impact.
BUG=chrome-os-partner:25043
TEST=Manual on Rambi. Verify RAM_ID GPIOs on test unit are read with
identical values as before.
BRANCH=Rambi.
Change-Id: I2f76395064ea6e4170b2eaad6e67bfc1aa22b54e
Reviewed-on: https://chromium-review.googlesource.com/182934
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Apply the SOC thermal settings from DPTF reference code for
SdpProfile=4 and adjust graphics PUNIT setting to match.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=boot on rambi and check for valid GPU power values from DPTF
Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther
Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Sometimes the SuperIO seems to provide wrong readings, especially early
on after a resume from suspend. This will cause the system to power off.
If that happens, wait for 1s and read again, to make sure the high
temperature value was not just a flaky read.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=Boot tested on Panther.
Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/182188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Though the limited documentation indicates the default is
0 for the gfx_turbo_disable bit, in practice that isn't
true. Knock down the gfs_turbo_disable bit to enable
graphics turbo mode.
BUG=chrome-os-partner:25044
BRANCH=baytrail
TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG.
Noted that bit 7 was set to 0.
Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Codec and ALS both have interrupt sources that can be configured.
The ALS kernel driver currently does not try to use it but the codec
driver does for things like jack detect.
ACPI Devices are added, but as with other ACPI devices the HID may
need to be updated once more official strings are decided.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: build and boot on rambi and check for functional lightsensor
Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182366
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This code should have been BSD licensed but was checked in with a GPL license.
BUG=chrome-os-partner:24957
TEST=Built libpayload for nyan.
BRANCH=None
Change-Id: Ic939fd21710c1d52b57b84d3038ec0c0ce4443cd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/182344
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
On baytrail, it appears that the turbo disable setting is
actually building-block scoped. One can see this on quad
core parts where if enable_turbo() is called only on the
BSP then only cpus 0 and 1 have turbo enabled. Fix this
by calling enable_turbo() on all non-bsp cpus.
BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and booted rambi. All cpus have bit 38 set to 0
in msr 0x1a0.
Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182406
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
