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a6b85ad950
This adds the very basic top-level support for determining the system wake source from ACPI. It only implements the _SWS method in the _SB scope which just returns a bit index into the PM1 status register for the first fixed functional block. This can be used to determine wake source of RTC or Power Button but does not help determine wake source for USB or GPIO. The ACPI spec says to return -1 if no source can be determined from PM1 status register. BUG=chrome-os-partner:8127 BRANCH=baytrail TEST=build and boot on rambi 1) Test resume from S3 by RTC: ACPI System Wake Source is PM1 Index 10 (bit 10 is RTC_STS in ACPI spec, ACPI_EVENT_RTC in kernel) 2) Test resume from S3 by power button: ACPI System Wake Source is PM1 Index 8 (bit 8 is PWRBTN_STS in ACPI spec, ACPI_EVENT_POWER_BUTTON in kernel) 3) Test resume from S3 by USB: ACPI System Wake Source is PM1 Index -1 Change-Id: Ifc5c0867f82cf291af157537b8c13fe44923d8f5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183333 Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| COMMIT-QUEUE.ini | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| PRESUBMIT.cfg | ||
| README | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.