We found that our UI resume time will exceed using G2 touch panel. After discussing with vendor they suggested to reduce the stop delay time to 150ms. We can get pass result after this modification. Please see b/468147191 for more details.
BUG=b:468147191
TEST=Pass UI Resume test with G2 touch panel
Change-Id: Iec78e27c4716e3442babad4f377efccb26773183
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for the Quenbi and Quartz
models. These Qualcomm-based boards require State of Charge (SoC) to be
calculated from dynamic battery metrics because the standard charge
state command is restricted during certain active power states.
Additionally, add platform_dump_battery_soc_information() to romstage
to log the battery percentage early in the boot process. This helps
with debugging power-related issues during the early boot sequence
when serial console is enabled.
Details:
- Select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for Quenbi and Quartz.
- Call the SoC dump in platform_romstage_main() if CONSOLE_SERIAL is on.
BUG=none
TEST=Boot Quenbi/Quartz and verify "Battery state-of-charge X" appears
in the romstage serial console logs.
Change-Id: I6184762140884762140884762140884762140884
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90619
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On certain platforms, such as Qualcomm X1P42100 (Hamoa), the AP cannot
successfully execute the standard CHARGE_STATE_CMD_GET_STATE host
command while in the S0 power state. This is typically due to hardware
arbitration or access restrictions to the battery fuel gauge bus during
active operating states.
This patch introduces a mechanism to fallback to manual State of Charge
(SoC) calculation using dynamic battery metrics:
1. Add EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC Kconfig: Allows platforms
to opt-in to manual SoC calculation.
2. Refactor existing logic: The standard command is moved to an internal
static helper google_chromeec_read_batt_state_of_charge_cmd().
3. Unified API: google_chromeec_read_batt_state_of_charge() now switches
between the standard command and the raw/dynamic calculation at
compile-time based on the Kconfig selection.
By using ec_cmd_battery_get_dynamic(), the AP retrieves cached telemetry
from the EC. This avoids triggering synchronous bus transactions to the
battery, ensuring SoC data is available even when direct fuel gauge
access is restricted.
BUG=none
BRANCH=none
TEST=Build for Hamoa and verify SoC is correctly calculated via the
dynamic info path. Verify standard platforms still use the charge
state command path.
Change-Id: I4928017362140884762140884762140884762140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement google_chromeec_read_batt_state_of_charge_raw() to
calculate the battery percentage using raw capacity metrics.
Unlike the standard charge state command, this function retrieves data
via EC_CMD_BATTERY_GET_DYNAMIC. It manually calculates the State of
Charge (SoC) by comparing remaining_capacity against full_capacity.
This provides a fallback mechanism for platforms where the high-level
CHARGE_STATE_CMD_GET_STATE command is not implemented or when working
directly with the fuel gauge's dynamic data cache.
Includes:
- Zero-capacity check to prevent division by zero.
- 100% clamping to handle fuel gauge rounding/calibration drift.
Change-Id: I86d6313884762140884762140884762140884762
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90615
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement google_chromeec_read_batt_state_of_charge() to retrieve the
current battery percentage from the Embedded Controller.
The function uses the CHARGE_STATE_CMD_GET_STATE host command to fetch
the State of Charge (SoC) as calculated by the EC's fuel gauge logic.
This provides a high-level percentage (0-100) suitable for power
management decisions or UI display.
Change-Id: Iec88476214088476214088476214088476214088
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This power resource is valid in S5, so correct the advertised level.
Change-Id: I208182a7633c03d818a5b8892d305e3bcd5b835f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This power resource is valid in S5, so correct the level that is
set. This makes it match the reference code, and the CNVi Bluetooth
power resource.
Change-Id: I430cafafc0326dc189a337bf2b67cf200afc4f17
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90610
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluetooth only signal wake while in USB suspend (D2). It is not possible
for it to wake when in D3 (low-power mode) so D3 is incorrect.
Change-Id: I1c2052507dfae235140e667b9a5580b4a7a8cb5d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90609
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code left Bluetooth disabled if it times out during reset.
Following the flow of the reference code, re-enable it to avoid it
ending up "stuck" off.
Change-Id: Ib1c49f28ec13068d9d7e59841ae35d1d26c30770
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90607
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The saved error values were reversed, so correct these.
This isn't a functional change, as the value isn't used in ACPI.
Change-Id: I9d3abcb4b17c36d33f2660e5d20fd5e6fb15fc34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Both ASRock H110 Pro BTC+ and ASRock Q1900-ITX have their vendor name
spelled as ASRock listed by Memtest86+ when ran on their OEM BIOS. This
patch will restore that vendor name casing behaviour when Memtest86+ is
run from a corebooted port of these mainboards. Cannot verify for the
current mainboards in the repository but this casing is also consistent
with the casing used on the vendor website: www.asrock.com
Change-Id: Icca8a0c0cba4e093a64cc26996de1fb34ee60089
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add new memory type CB_MEM_TAG to coreboot_tables.h. This definition was
missing when CB:90470 was instroduced.
Change-Id: I76990706649bc1a4e45478760446dff40e871d77
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90612
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the value of BIAS_POWER_ON in the MT8189 dptx_reg.h file,
by changing it from 0x01 to 0x03. The MT8189 needs to enable one
more power register bit to make bias work rather than timeout.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: I345b23af0b5802e71d6d7bcd3fe806aaa71cc3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Commit de4148888c ("tests: Disable generation of lcov HTML") only
disabled the HTML generation for the coreboot tests, but not for
libpayload tests. So do it here as well.
Change-Id: I35458345c81de8b9936a17bb6fb5670b29a6d05e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90608
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces ChromeOS-specific logic to the Panther Lake SoC
TDP selection. It addresses the need to correctly set the CPU TDP to 15
W without having to set the desired_tdp flag in each mainboard device
tree.
BUG=b:465698900
Change-Id: Ibaee530159f7e3b94aac16ab50b749cb161cee10
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a mechanism to configure the Thermal Design Power
(TDP) for Panther Lake, allowing board designers to override the default
TDP reported by hardware and select the value that matches their
specific board requirements.
Previously, the TDP value was determined solely by the hardware, which
limited flexibility for platforms that support multiple TDP options. By
adding a new field to the `soc_intel_pantherlake_config` structure and
implementing the `soc_get_cpu_tdp()` function, this change enables
boards to opt out of the default TDP and specify a custom value.
BUG=b:465698900
Change-Id: I6e401c2c7d7d0cda24fa07ec024813874fac3ed5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90150
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update PL1 override values from a fixed value to zero, indicating that
the platform should use the default TDP value. This change allows the
common code to dynamically set PL1 according to the specific TDP SKU,
improving flexibility and ensuring correct power limit configuration
across different hardware variants.
Previously, PL1 was hardcoded to 15 for some SKUs, which could lead to
instabilities for SKUs with different TDP requirements.
TEST=No instability was observed on certain Fatcat SKUs.
Change-Id: Ibfb6b52aa15ad66740abc39f6f869dfa5e90de3c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Ryu, Jamie M <jamie.m.ryu@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Checkpatch emits the following warning about autoport-generated code:
WARNING: space prohibited between function name and open parenthesis '('
So, simply get rid of that space.
Change-Id: If52e3d56c6b254efb61c70c8e482014dd4208172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
8.5MB to accommodate APDP, Ramdump and ADSP-lite images. A 5MB
estimated size of QTEE image is also taken into account to avoid future
resizing.
Size required for QTEE:
Current size -> 2776K, Estimated size -> 5120K (5MB)
Additional size needed -> 5120K-2776K = 2344K
Size required for new images:
Ramdump - 449K
APDP - 0.7K
ramdump_meta - 0.1K
apdp_meta - 1.4K
ADSP_Lite - 1192K
Total = 1643K
Additional size needed (QTEE + new images):
2344K+1643K = 3987K
Current Layout of FW_MAIN_A/B slots:
Total size - 4608K (4.5MB)
Used size - 4126K
Free size - 482K
Additional size needed (excluding free size):
3987K-482K = 3505K
Total size of FW_MAIN_A/B slots:
4608K+3505K = 8133K
An additional buffer of 591K is included in the final size to
provide room for increase in size of other blobs. So,
Final size of FW_MAIN_A/B slots:
8133K+591K = 8704K (8.5MB).
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I3b3ba5c4bf8b5d3830174a890ea7cd089e3f274f
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90594
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pic_width and pic_height fields of dsc_config are equivalent to
edid.mode.ha and edid.mode.va, respectively. To remove duplicate
information in panel_serializable_data, remove these two fields from
dsc_config.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I7f1dd4b431a610fa928b29da420b0c0e0bef5fcc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90561
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pic_width and pic_height in the dsc_config struct are equivalent to
edid.mode.ha and edid.mode.va. The duplicate information should be
removed from the panel_serializable_data struct, by removing from
dsc_config. To do that, replace references of dsc_config.pic_width with
edid.mode.ha in the MT8196 code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Id1014886851a999ccdfec7ec86df2e7341ba9ffd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90560
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
We'd like to replace dsc_cfg->pic_width with edid->mode.ha in MT8196's
dsc_configure_registers() and then deprecate the 'pic_width' field. To
do that, we will first need to pass the edid struct pointer from
mtk_ddp_mode_set() all the way to that function.
Currently mtk_ddp_mode_set() is in the MediaTek common code, which calls
SoC's mtk_ddp_soc_mode_set(), but the edid isn't passed. To simplify the
edid pointer passing, drop mtk_ddp_soc_mode_set() and replace it with
SoC's mtk_ddp_mode_set(). To minimize the duplicate code of calculating
vrefresh, introduce mtk_get_vrefresh() to the display API, and reference
it from SoC's code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Ifb84c6b954dde2f25c3ac491a5392b7725c13a43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90559
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Pass dsi_regs to mtk_dsi_cphy_timing() to be consistent with other DSI
APIs and mtk_dsi_dphy_timing(). This also supports C-PHY with dual
channel, although there is currently no such a device.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I81805aa181c46fb29c70d18553dbf0c0c06c2888
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90558
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Move dpm_init() and spm_init() from mainboard_init() in rauru to
soc_init() in mt8196. This centralizes the power management
initialization within the SoC-specific code.
BUG=none
TEST=Build pass, boot ok.
Change-Id: Ic2914fd0fc85032c96ce076416e9b9c46fe19e0d
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90550
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
That parameter was mistakenly added here while trying to silent lcov
complaints. Drop it again since it's not supported here.
Change-Id: I77bed4ebb7d3ef6daea39c812bacfcad7a72aee7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add missing configuration items for rex variants to have functional
MIPI cameras under Windows/mainline Linux:
- Add IPUA device to graphics device configuration
- Add sensor_name register to sensor device configurations
Screebo was missing the gfx/generic configuration for all other display
outputs present in other variants, so add that as well.
TEST=build/boot Win11/Linux on karis and screebo, verify MIPI camera
functional under both OSes using the standard driver stack.
Change-Id: I14ec0efd88c43ca94ebde2be4652775bcb6d73c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Ensure all mipi_camera sensor configurations have both ssdb.lanes_used
and ssdb.link_used defined, and that these values correctly match the
corresponding (known good) CIO2 IPU port configuration:
- ssdb.lanes_used must match cio2_lanes_used = {x} for CAMx
- ssdb.link_used must match cio2_prt[x] for CAMx
Change-Id: Ifbf22c69d29c71138b7f59f08782d90425a09e30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The issues still appears even after commit 65833355ca ("tests: Disable
gcov warnings"). So, disable the HTML generation completely until the
issue is figured out.
Change-Id: I683889ff8a0769697154079f99fe1d6ff9773281
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This adds a few items which were merged after the preliminary release
notes were merged, and updates the statistics for actual release tag.
Change-Id: I3b59568a67a3caa553c5f409edfed3053c1d4b7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot starlite_adl, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I0fd28e38f5d3ad1e4db33fa3ab075929044ac831
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a CFR option to expose the newly-added EC control to set the charge
LED brightness (normal/dim/off).
TEST=build/boot starlabs/lite_adl, verify charge LED control via CFR
Change-Id: I090437e8de2fd65bfad93a2037fd9346347e9fc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90566
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).
TEST=build/boot starfighter_mtl, verify LED control via CFR
Change-Id: I2af8372f923f92af62e48da77d4bddb87ab1eba0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90565
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).
TEST=build/boot starbook_mtl, verify LED control via CFR
Change-Id: I7e1fe4efaab4327c8b95b108a9014e50058d6ed4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90564
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add support for controlling charge LED brightness similar to the
existing power LED brightness control. This includes:
- New Kconfig option EC_STARLABS_CHARGE_LED
- Charge LED CFR option in cfr.h
- Implementation in ite.c using shared led_brightness array
- ECRAM_CHARGE_LED register definition
Refactor LED brightness enum values into shared led_brightness array
for reuse between power and charge LED controls.
EC changes for charge LED brightness
TEST=build/boot starlabs/lite_adl and verify LED control via CFR
Change-Id: I0f243d666e1fdc7d6df9859bb1cdcf460b6029ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This fixes the duplicate ddr6 entry which should have been ddr5.
Change-Id: I3bbee8a2fbacc7fa057e225fcfe307877b4f2716
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The mtk_ddp_ovlsys_start function is updated to take edid and path
as arguments. This allows the function to configure the framebuffer
address and overlay for DISP_PATH_DUAL_MIPI path.
BUG=b:319511268
TEST=cherry pick CB:90504 and manual enable BMP_LOGO related configs.
The logo is drawn in the ramstage.
Change-Id: I60809f7062907617f2af1badcad9f53477911020
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add an option to lock the regions BOOTBLOCK and COREBOOT, leaving the
regions TOPSWAP and COREBOOT_TS for updates in an Intel Top Swap
redundancy scenario.
This means that the user can now write and choose to boot from the
update regions, selecting the attempt_slot_b CMOS option, and there is
a protected golden copy of the entire firmware, that cannot be
overwritten and can be reverted to by resetting CMOS.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: Ia6dea22c41e2fc778af6ca7049b72c92686ec85f
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Before CPU resume, it is necessary to reinitialize the MTE-related
settings of booker in MCUPM to prevent the loss of booker
configurations after resume.
BUG=b:467186613
TEST=Build pass, Verify S/R OK on Navi and Sapphire.
Change-Id: Ieaf4c2ea0f8a5c372a5dbf4d0f6c44fbd978e6a6
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90546
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.
Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map(). This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.
The branching is done on the state of RTC BUC to always use the current
bootblock. Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.
Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
- recognize both "BOOTBLOCK" and "TOPSWAP" regions
- recognize both "COREBOOT" and "COREBOOT_TS" regions
- reset metadata cache before processing each region as cache may now
be invalid
SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.
This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.
Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a correction of CB:89570 (commit 04ea4724e2 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")). It wasn't obvious
that CBFS verification depends on bootblock being added first (otherwise
cbfstool considers CBFS verification to be disabled because anchor is
part of a bootblock). Correct this and add a comment for anyone else
who might edit this code in the future.
The issue manifested itself in build failing to perform CBFS
verification via cbfstool when the firmware was built with
CBFS_VERIFICATION enabled.
Change-Id: If775480394270fc05206cde0707c511b126265d3
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90436
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Take advantage of cbfstool's ability to operate on multiple regions and
introduce a variable with a list of main CBFS regions: it's just
"COREBOOT" in most cases, but becomes "COREBOOT,COREBOOT_TS" when Top
Swap update mechanism is enabled (see [0]).
This is meant to simplify Makefiles by avoiding extra branches in
existing and future changes.
[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: If537d0d21a2867fafc2241ea9a0b4c0c6ca290a8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90435
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is a correction of CB:89570 (commit 04ea4724e2 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")) which has FITs in both
BOOTBLOCK and TOPSWAP point at microcode in COREBOOT region.
This can be tested by comparing outputs of
build/util/cbfstool/ifittool -f build/coreboot.rom -r TOPSWAP -D
and
build/util/cbfstool/ifittool -f build/coreboot.rom -r BOOTBLOCK -D
with microcode addresses as shown by
uefitool build/coreboot.rom
The addresses in two regions must not be identical and their last six
hex digits must match what uefitool shows in "Base:" field (not
"Offset:").
Change-Id: Ie37aee7a26be18d1a4d8993afd2a2484c38c0b1e
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
The addition provides a way to select USE_OPTION_TABLE for a mainboard
which depends on the CMOS backend for options. This is needed to
support update mechanism based on Top Swap that permits recovery via a
CMOS reset (see [0]). The indirection is necessary because
USE_OPTION_TABLE is part of a `choice`.
[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: I9e8f044077a5158650627a305c352cc9de578293
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90433
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
